HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE
A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
1 - 4 . (canceled)
5 . A semiconductor device comprising:
first, second, third, and fourth high-voltage transistors on a main surface of a semiconductor substrate, the first and second high-voltage transistors being adjacent to each other in a gate-width direction, the third and fourth high-voltage transistors being adjacent to each other in the gate-width direction, the first and third high-voltage transistors being adjacent to each other in a gate-length direction, and the second and fourth high-voltage transistors being adjacent to each other in the gate-length direction,
wherein the first high-voltage transistor includes a first gate electrode and a first gate electrode contact on the first gate electrode,
the second high-voltage transistor includes a second gate electrode and a second gate electrode contact on the second gate electrode,
the third high-voltage transistor includes a third gate electrode and a third gate electrode contact on the third gate electrode, and
the fourth high-voltage transistor includes a fourth gate electrode and a fourth gate electrode contact on the fourth gate electrode; and
a shielding gate provided on an element isolation region such that the shielding gate extends across a first portion of the element isolation region between the first and third high-voltage transistors and a second portion of the element isolation region between the second and fourth high-voltage transistors.