IP Library › Granted Patent US 11,940,659
Granted Patent B2
US 11,940,659 · App. 17/460,789 · Granted Mar 26, 2024

Optical integrated circuit structure including edge coupling protective features and methods of forming same

Inventors: Chen-Hao Huang (Taoyuan, TW); Hau-Yan Lu (Hsinchu, TW); Sui-Ying Hsu (New Taipei, TW); Yuehying Lee (Hsinchu, TW); Chien-Ying Wu (Hsinchu, TW); Chia-Ping Lai (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
G02B6/4248G02B6/12G02B6/12002G02B6/12004G02B6/136G02B6/4206G02B6/4274H01L23/53228G02B6/30G02B6/4228G02B6/4236H01L21/30604H01L21/3065H01L21/31116H01L23/5226H01L23/585
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Quick Facts
Patent No.
US 11,940,659
App. No.
17/460,789
Granted
Mar 26, 2024
Kind
B2
Abstract

An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

Claims (49)

1. An optical integrated circuit (IC) structure comprising:

a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;

a semiconductor layer disposed on the substrate;

a dielectric structure disposed on the semiconductor layer;

an interconnect structure disposed in the dielectric structure;

a plurality of vents that extend through a coupling region of the dielectric structure, wherein the plurality of vents each expose the undercut;

a fiber cavity that extends through the coupling region of the dielectric structure and exposes the fiber slot; and

a barrier ring disposed in the dielectric structure, wherein the barrier ring surrounds the interconnect structure and is routed around a perimeter of the coupling region.

2. The IC structure of claim 1 , wherein the barrier ring separates the interconnect structure from the plurality of vents and the fiber slot, and the barrier ring is configured to prevent contaminants from diffusing into the interconnect structure.

3. The IC structure of claim 1 , wherein the barrier ring comprises a metal.

4. The IC structure of claim 1 , wherein the barrier ring and the interconnect structure comprise copper or a copper alloy.

5. The IC structure of claim 1 , wherein the barrier ring has a thickness of at least 10 microns.

6. The IC structure of claim 1 , wherein the substrate comprises an optical waveguide that is disposed over the undercut, and the optical waveguide extends between the plurality of vents to the fiber slot.

7. The IC structure of claim 1 , further comprising a barrier layer disposed on:

vent sidewall surfaces of each of the plurality of vents;

an undercut top surface, an undercut bottom surface, and an undercut side surface;

a fiber cavity sidewall surface; and

a fiber slot bottom surface and a fiber slot sidewall surface,

wherein the barrier layer comprises a barrier layer material.

8. The IC structure of claim 7 , wherein the barrier layer material comprises a dielectric material.

9. The IC structure of claim 8 , wherein the barrier layer has a thickness of at least 10 microns.

10. An optical integrated circuit (IC) structure comprising:

a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot, wherein the undercut comprises an undercut top surface, an undercut bottom surface, and an undercut side surface, and the fiber slot comprises a fiber slot bottom surface and a fiber slot sidewall surface;

a semiconductor layer disposed on the substrate;

a dielectric structure disposed on the semiconductor layer;

an interconnect structure disposed in the dielectric structure;

a plurality of vents that extend through a coupling region of the dielectric structure, wherein the plurality of vents each expose the undercut and comprise vent sidewall surfaces;

a fiber cavity that extends through the coupling region of the dielectric structure and exposes the fiber slot, wherein the fiber cavity comprises a fiber cavity sidewall surface; and

a barrier layer disposed on the vent sidewall surfaces of the plurality of vents, the undercut top surface, the undercut bottom surface, the undercut side surface, the fiber cavity sidewall surface, the fiber slot bottom surface and the fiber slot sidewall surface.

11. The IC structure of claim 10 , wherein the barrier layer covers internal surfaces of the plurality of vents, the undercut, the fiber cavity, and the fiber slot.

12. The IC structure of claim 10 , wherein the barrier material comprises a dielectric material.

13. The IC structure of claim 10 , wherein the barrier layer has a thickness of at least 50 nanometers.

14. The IC structure of claim 10 , wherein the substrate comprises an optical waveguide that is disposed over the undercut and that extends between the plurality of vents to the fiber slot.

15. The IC structure of claim 10 , further comprising a barrier ring disposed in the dielectric structure, wherein the barrier ring surrounds the interconnect structure and contacts the barrier layer on opposing sides of the fiber cavity.

16. The IC structure of claim 15 , wherein the barrier ring comprises a metal.

17. The IC structure of claim 16 , wherein the barrier ring and the interconnect structure comprise copper or a copper alloy.

18. An optical integrated circuit (IC) structure comprising:

a substrate comprising a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot;

a semiconductor layer disposed on the substrate;

a dielectric structure disposed on the semiconductor layer;

an interconnect structure disposed in the dielectric structure;

vents that extend through the dielectric structure to expose the undercut;

a fiber cavity that extends through the dielectric structure and the semiconductor layer to expose the fiber slot; and

a barrier ring disposed in the dielectric structure and surrounding the interconnect structure.

19. The IC structure of claim 18 , further comprising a barrier layer disposed on surfaces of the vents, the undercut, and the fiber slot.

20. The IC structure of claim 18 , wherein:

the undercut has a depth ranging from about 30 to about 70 μm;

the fiber slot has a depth ranging from about 60 to about 100 μm; and

barrier ring is disposed between the interconnect structure and the vents and the fiber cavity.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2021
From: HUANG, CHEN-HAO; LU, HAU-YAN; HSU, SUI-YING; LEE, YUEHYING; WU, CHIEN-YING; LAI, CHIA-PING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 057327/0225 →
Continuity (1)
Related Publication 20230069212A1 · Mar 2, 2023
Cited By (1)
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