Seal ring designs supporting efficient die to die routing

1. A chip structure comprising:

a semiconductor substrate;

a first front-end-of-the-line (FEOL) die area of a first die patterned into the semiconductor substrate; and

a back-end-of-the-line (BEOL) build-up structure including:

a lower metallization layer, an upper metallization layer, and a first metallization layer spanning over the first FEOL die area, wherein the first metallization layer is between the lower metallization layer and the upper metallization layer;

a split metallic seal structure including an inner metallic seal and an outer metallic seal arranged with one of the inner metallic seal and the outer metallic seal being a lower metallic seal overlapping the lower metallization layer and another of the inner metallic seal and the outer metallic seal being an upper metallic seal overlapping the upper metallization layer;

wherein portions of the inner metallic seal and the outer metallic seal are both formed in the first metallization layer; and

a through seal interconnect extending from the first FEOL die area and into a scribe region laterally outside of the outer metallic seal; and

wherein the split metallic seal structure is coupled to a charge source to control potential of at least one of the inner metallic seal and the outer metallic seal.

2. The chip of claim 1 wherein each of the inner metallic seal and the outer metallic seal include a plurality of metal filled trenches and metal wiring layers.

3. The chip of claim 1 , wherein the charge source comprises a charge source routing connected with the outer metallic seal.

4. The chip of claim 3 , wherein the charge source routing comprises a metal plane spanning across the outer metallic seal.

5. The chip of claim 4 , wherein the metal plane is denser laterally inside the outer metallic seal than laterally outside of the outer metallic seal.

6. The chip of claim 4 , wherein the through seal interconnect includes wiring that spans directly over the metal plane.

7. The chip of claim 6 , wherein the wiring includes a vertical jog that extends into a metallization layer including the metal plane of the charge source routing.

8. The chip of claim 1 , wherein the first FEOL die area includes an input/output region and a core region.

9. The chip of claim 8 , wherein the through seal interconnect is connected to a buffer in the input/output region.

10. The chip of claim 8 , wherein the through seal interconnect is connected to a buffer in a wrapper region adjacent the core region.

11. The chip of claim 8 , wherein the through seal interconnect is connected to a buffer in the scribe region.

12. The chip of claim 8 , wherein the inner metallic seal is located between the input/output region and the core region.

13. The chip of claim 12 , wherein the outer metallic seal is located in the scribe region.

14. The chip of claim 1 , wherein the outer metallic seal is the lower metallic seal and the inner metallic seal is the upper metallic seal.

15. The chip of claim 14 , further comprising a second inner metallic seal wherein the second inner metallic seal is a second lower metallic seal.

16. The chip of claim 14 , wherein the outer metallic seal is located in the scribe region.

17. The chip of claim 1 , wherein the through seal interconnect includes extends over the outer metallic seal.

18. The chip of claim 17 , wherein the through seal interconnect includes a jog between multiple metal layers in the scribe region.

19. The chip of claim 1 , further comprising a chip edge in the scribe region, and a terminal end of the through seal interconnect at the chip edge.

20. The chip of claim 1 , wherein the through seal interconnect extends from the scribe region to a second FEOL die area of a second die patterned into the semiconductor substrate.