Apparatus, method, and system for power consumption management of system-on-chip
In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.
1. A system-on-chip (SOC) comprising:
a processing unit comprising a plurality of processor cores, and configured to perform at least one processing operation at an operating frequency;
a controller configured to increase the operating frequency when at least one of the plurality of processor cores is inactive; and
a control logic configured to receive a warning signal from a power management integrated circuit (PMIC) and generate a control signal for changing the operating frequency;
wherein the SOC is configured to perform a frequency step-down operation if the warning signal is continuously activated for equal to or more than a predetermined time interval,
wherein the warning signal is generated by the PMIC based on a determination by the PMIC that power consumption of the SOC exceeds a predetermined power consumption, and
wherein the frequency step-down operation comprises:
decreasing the operating frequency by a first predetermined amount until the warning signal is deactivated;
after the warning signal is deactivated, increasing the operating frequency by the first predetermined amount;
based on the warning signal being reactivated, decreasing the operating frequency by the first predetermined amount; and
after the reactivated warning signal is deactivated, increasing the operating frequency by a second predetermined amount, wherein the second predetermined amount is less than the first predetermined amount.
2. The SOC of claim 1 , wherein the PMIC is configured to transmit the warning signal directly to the control logic; and
wherein the warning signal indicates that the power consumption of the SOC is exceeding the predetermined power consumption.
3. The SOC of claim 1 , wherein the SOC is configured to perform multiple frequency step-down operations, wherein the frequency step-down operation comprises decreasing the operating frequency by a predetermined amount.
4. The SOC of claim 3 , wherein the multiple frequency step-down operations are performed until the warning signal is deactivated.
5. The SOC of claim 1 , wherein the warning signal is generated at the PMIC when present power consumption of the plurality of processor cores exceeds a predetermined power.
6. The SOC of claim 1 , wherein the control logic is located inside the processing unit.
7. The SOC of claim 1 , wherein the control logic is located outside the processing unit.
8. The SOC of claim 1 , wherein the PMIC is configured to provide the warning signal to the SOC through a channel separated from a power supply channel or a power management control channel.
9. A system comprising:
a processing unit comprising a plurality of processor cores, and configured to perform at least one processing operation at an operating frequency;
a power management integrated circuit (PMIC) configured to supply power to the processing unit based on a power management control signal received from the processing unit and provide a warning signal to a control logic based on a determination by the PMIC that present power consumption of the processing unit exceeds predetermined power; and
the control logic configured to receive the warning signal from the PMIC and generate a control signal which is transmitted to the processing unit;
wherein, in response to the control signal, the processing unit is configured to generate an interrupt to instruct dynamic voltage and frequency scaling (DVFS) control program to adjust the operating frequency, and
wherein the DVFS control program comprises:
decreasing the operating frequency by a first predetermined amount until the warning signal is deactivated;
after the warning signal is deactivated, increasing the operating frequency by the first predetermined amount;
based on the warning signal being reactivated, decreasing the operating frequency by the first predetermined amount; and
after the reactivated warning signal is deactivated, increasing the operating frequency by a second predetermined amount, wherein the second predetermined amount is less than the first predetermined amount.
10. The system of claim 9 , wherein the control logic is configured to generate the control signal if the warning signal is continuously activated for equal to or more than a predetermined time interval.
11. The system of claim 9 , wherein the control logic is configured to generate the control signal immediately after the warning signal is activated.
12. The system of claim 9 , wherein the PMIC is configured to transmit the warning signal directly to the control logic.
13. The system of claim 9 , wherein the processing unit is configured to perform a frequency step-down operation; and
wherein the frequency step-down operation comprises decreasing the operating frequency by a predetermined amount.
14. The system of claim 13 , wherein the processing unit is configured to perform multiple frequency step-down operation until the warning signal is deactivated.
15. The system of claim 9 , wherein the control logic is located inside the processing unit.
16. The system of claim 9 , wherein the control logic is located outside the processing unit.
17. The system of claim 9 , wherein the PMIC is configured to provide the warning signal to the processing unit through a channel separated from a power supply channel or a power management control channel.
18. A system comprising:
a processing unit comprising a plurality of processor cores, and configured to perform at least one processing operation at an operating frequency;
a power management integrated circuit (PMIC) configured to provide supply power and a warning signal to the processing unit; and
a power management unit (PMU) configured to monitor power consumption of the processing unit, generate a power management control signal for controlling the supply power, and transmit the power management control signal to the PMIC;
wherein the PMIC is configured to provide the warning signal and the supply power through separate channels;
wherein the processing unit is configured to perform dynamic voltage and frequency scaling (DVFS) in response to the warning signal,
wherein the warning signal is generated by the PMIC based on a determination by the PMIC that the power consumption of the processing unit exceeds a predetermined power consumption, and
wherein the DVFS control program comprises:
decreasing the operating frequency by a first predetermined amount until the warning signal is deactivated;
after the warning signal is deactivated, increasing the operating frequency by the first predetermined amount;
based on the warning signal being reactivated, decreasing the operating frequency by the first predetermined amount; and
after the reactivated warning signal is deactivated, increasing the operating frequency by a second predetermined amount, wherein the second predetermined amount is less than the first predetermined amount.