Non-planar transistor devices and methods of manufacturing thereof

1. A method for making a semiconductor device, comprising:

forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another;

forming a dummy gate structure, over the fin structure, that extends along a second direction perpendicular to the first direction; and

forming a gate spacer extending in the second direction along respective upper sidewall portions of the dummy gate structure and separated by a portion of the dummy gate structure from a topmost one of the plurality of channel layers, thereby defining a first distance between a bottom surface of the gate spacer and a top surface of the topmost one of the plurality of channel layers by the portion of the dummy gate structure;

wherein the first distance is similar to a second distance that separates neighboring ones of the plurality of channel layers.

2. The method of claim 1 , wherein the second distance is equal to a thickness of each of the plurality of sacrificial layers.

3. The method of claim 1 , further comprising:

recessing portions of the fin structure that are disposed on opposite sides of the gate spacer;

removing a lower portion of the dummy gate structure;

forming source/drain structures in the recessed portions of the fin structure; and

replacing the plurality of sacrificial layers and the dummy gate structure with an active gate structure.

4. The method of claim 3 , prior to the step of forming source/drain structures, further comprising:

replacing respective end portions of each of the plurality of sacrificial layers with an inner spacer.

5. The method of claim 1 , wherein the step of forming a fin structure further comprises overlaying the fin structure with a hardmask layer, and wherein the hardmask layer and the dummy gate structure include a similar material.

6. The method of claim 5 , further comprising:

retaining the hardmask layer while forming the dummy gate structure; and

subsequently to forming the dummy gate structure, recessing portions of the hardmask layer that are not overlaid by the dummy gate structure such that the first distance is defined by a thickness of a remaining portion of the hardmask layer.

7. The method of claim 5 , further comprising removing the hardmask layer prior to forming the dummy gate structure such that the first distance is defined by a thickness of a lower portion of the dummy gate structure.

8. The method of claim 5 , further comprising:

retaining the hardmask layer while forming the dummy gate structure;

forming a first layer of the dummy gate structure;

recessing the hardmask layer and the first layer of the dummy gate structure at a similar etching rate, thereby forming a coplanar surface shared by the top surface of the topmost channel layer and a top surface of the first layer of the dummy gate structure;

forming a second layer of the dummy gate structure; and

replacing respective sidewall portions of the second layer of the dummy gate structure with the gate spacer.

9. The method of claim 5 , further comprising:

retaining the hardmask layer while forming the dummy gate structure; forming a first layer of the dummy gate structure;

recessing the hardmask layer and the first layer of the dummy gate structure at different etching rates, thereby causing a top surface of the topmost channel layer to be below a top surface of the first layer of the dummy gate structure;

forming a second layer of the dummy gate structure; and

replacing respective sidewall portions of the second layer of the dummy gate structure with the gate spacer.

10. A method for making a semiconductor device, comprising:

forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another; and

forming a gate spacer that extends along sidewalls of a patterned upper layer of a dummy gate structure, wherein the upper layer extends along a second direction perpendicular to the first direction, wherein the dummy gate structure is formed over a hardmask layer that is disposed over the fin structure, and wherein a thickness of a remaining portion of the hardmask layer is about equal to a distance separating neighboring ones of the plurality of channel layers;

wherein the gate spacer is either in contact with or separated from a topmost one of the plurality of channel layers.

11. The method of claim 10 , wherein the step of forming a gate spacer further comprises:

forming the dummy gate structure that comprises a blanket upper layer and a blanket lower layer over the hardmask layer;

etching the blanket upper layer to form the patterned upper layer;

recessing portions of the hardmask layer that are not overlaid by the patterned upper layer; and

forming the gate spacer such that the gate spacer is separated from the topmost channel layer with a remaining portion of the hardmask layer.

12. The method of claim 10 , wherein the step of forming a gate spacer further comprises:

removing the hardmask layer;

forming the dummy gate structure that comprises a blanket upper layer and a blanket lower layer over the fin structure;

etching the blanket upper layer to form the patterned upper layer; and

forming the gate spacer such that the gate spacer is separated from the topmost channel layer with a remaining portion of the blanket lower layer and/or a remaining portion of the patterned upper layer.

13. The method of claim 12 , wherein a thickness of the remaining portion of the blanket lower layer or the remaining portion of the patterned upper layer is about equal to a distance separating neighboring ones of the plurality of channel layers.

14. The method of claim 10 , wherein the step of forming a gate spacer further comprises:

forming a blanket lower layer of the dummy gate structure while retaining the hardmask layer;

recessing the hardmask layer and the blanket lower layer at a similar etching rate, thereby causing a top surface of the topmost channel layer to be below a top surface of the blanket lower layer;

forming a blanket upper layer of the dummy gate structure;

etching the blanket upper layer to form the patterned upper layer; and

forming the gate spacer such that the gate spacer is in contact with the topmost channel layer.

15. The method of claim 10 , wherein the step of forming a gate spacer further comprises:

forming a blanket lower layer of the dummy gate structure while retaining the hardmask layer;

recessing the hardmask layer and the blanket lower layer at different etching rates, thereby causing a top surface of the topmost channel layer to be below a top surface of the blanket lower layer;

forming a blanket upper layer of the dummy gate structure;

etching the blanket upper layer to form the patterned upper layer; and

forming the gate spacer such that the gate spacer is in contact with the topmost channel layer.

16. The method of claim 10 , wherein the hardmask layer and the dummy gate structure include a similar material.

17. The method of claim 10 , further comprising:

recessing portions of the fin structure that are disposed on opposite sides of the gate spacer;

patterning a blanket lower layer of the dummy gate structure based on the patterned upper layer;

forming source/drain structures in the recessed portions of the fin structure; and

replacing the plurality of sacrificial layers and the dummy gate structure with an active gate structure.

18. A semiconductor device, comprising:

a plurality of channel layers over a substrate, wherein the plurality of channel layers laterally extend along a first direction and are vertically separated from each other;

a dummy gate structure that extends along a second direction perpendicular to the first direction and wraps around each of the plurality of channel layers;

a gate spacer that extends along upper sidewalls of the dummy gate structure along the second direction; and

an inner spacer that is disposed below the gate spacer and between neighboring ones of the plurality of channel layers;

wherein the gate spacer is separated from a topmost channel layer of the plurality of channel layers by a portion of the dummy gate structure.

19. The semiconductor device of claim 18 , wherein a distance between a bottom surface of the gate spacer and a top surface of the topmost channel layer is about equal to a distance separating the neighboring ones of the plurality of channel layers.

20. The semiconductor device of claim 18 , wherein the distance separating the neighboring ones of the plurality of channel layers is equal to a thickness of each portion the inner spacer that is between neighboring ones of the plurality of channel layers.