3D memory semiconductor device and structure
A 3D memory device, the device including: a first vertical pillar, the first vertical pillar includes a transistor source; a second vertical pillar, the second vertical pillar includes the transistor drain, where the first vertical pillar and the second vertical pillar each functions as a source or functions as a drain for a plurality of overlaying horizontally-oriented memory transistors, where at least of one of the plurality of overlaying horizontally-oriented memory transistors is disposed between the first vertical pillar and the second vertical pillar, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following a same lithography step, and where the first vertical pillar includes metal.
1. A 3D memory device, the device comprising:
a first vertical pillar, said first vertical pillar comprises a transistor source; and
a second vertical pillar, said second vertical pillar comprises a transistor drain,
wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors,
wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate,
wherein each self-aligned gate is disposed atop of a self-aligned underlying gate,
wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region, and
wherein at least two of the self-aligned channel region of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprise direct connection.
2. The 3D memory device according to claim 1 ,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a self-aligned charge trap region, and
wherein said tunneling oxide region is thinner than 1 nm or does not exist, which enables said 3D memory device to operate at high speed.
3. The 3D memory device according to claim 1 , further comprising:
a plurality of self-aligned memory control circuits;
wherein said plurality of self-aligned memory control circuits provide a periodic memory refresh operation to said first plurality of self-aligned overlaying horizontally-oriented memory transistors.
4. The 3D memory device according to claim 1 ,
wherein said first vertical pillar comprises metal and does not comprise n+ type doped silicon.
5. The 3D memory device according to claim 1 , further comprising:
a third vertical pillar;
wherein said third vertical pillar and said second vertical pillar each comprise a source or comprise a drain for a second plurality of self-aligned overlaying horizontally-oriented memory transistors.
6. The 3D memory device according to claim 1 ,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned charge trap region.
7. A 3D memory device, the device comprising:
a first vertical pillar, said first vertical pillar comprises a transistor source; and
a second vertical pillar, said second vertical pillar comprises a transistor drain,
wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors,
wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate,
wherein each self-aligned gate is disposed atop of a self-aligned underlying gate,
wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region,
wherein at least two of the self-aligned channel region of said first plurality of self-aligned horizontally-oriented memory transistors comprise direct connection,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a self-aligned charge trap region, and
wherein said tunneling oxide region is thinner than 1 nm or does not exist, which enables said 3D memory device to operate at high speed.
8. The 3D memory device according to claim 7 , further comprising:
a plurality of self-aligned memory control circuits;
wherein said plurality of self-aligned memory control circuits provide a periodic memory refresh operation to said first plurality of self-aligned overlaying horizontally-oriented memory transistors.
9. The 3D memory device according to claim 7 ,
wherein said first vertical pillar comprises metal and does not comprise n+ type doped silicon.
10. The 3D memory device according to claim 7 , further comprising:
a third vertical pillar;
wherein said third vertical pillar and said second vertical pillar each comprise a source or comprise a drain for a second plurality of self-aligned overlaying horizontally-oriented memory transistors.
11. The 3D memory device according to claim 7 ,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned charge trap region.
12. The 3D memory device according to claim 7 ,
wherein said first vertical pillar and said second vertical pillar each comprise a filled cylindrical shape.
13. The 3D memory device according to claim 7 ,
wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a unique channel region, and
wherein each of said unique channel regions is isolated from each other.
14. A 3D memory device, the device comprising:
a first vertical pillar, said first vertical pillar comprises a transistor source; and
a second vertical pillar, said second vertical pillar comprises a transistor drain,
wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors,
wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate,
wherein each self-aligned gate is disposed atop of a self-aligned underlying gate,
wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region,
wherein at least two of the self-aligned channel region of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprise direct connection, and
wherein said first vertical pillar comprises metal and does not comprise n+ type doped silicon.
15. The 3D memory device according to claim 14 ,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a self-aligned charge trap region, and
wherein said tunneling oxide region is thinner than 1 nm or does not exist, which enables said 3D memory device to operate at high speed.
16. The 3D memory device according to claim 14 , further comprising:
a plurality of self-aligned memory control circuits;
wherein said plurality of self-aligned memory control circuits provide a periodic memory refresh operation to said first plurality of self-aligned overlaying horizontally-oriented memory transistors.
17. The 3D memory device according to claim 14 , further comprising:
a third vertical pillar;
wherein said third vertical pillar and said second vertical pillar each comprise a source or comprise a drain for a second plurality of self-aligned overlaying horizontally-oriented memory transistors.
18. The 3D memory device according to claim 14 ,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned charge trap region.
19. The 3D memory device according to claim 14 ,
wherein said first vertical pillar and said second vertical pillar each comprise a filled cylindrical shape.
20. The 3D memory device according to claim 14 ,
wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a unique channel region, and
wherein each of said unique channel regions is isolated from each other.