Thin film transistor based light sensor

1. A circuit, comprising:

a first transistor with a first channel region, a first source/drain region disposed on a first end portion of the first channel region, and a second source/drain region disposed on a second end portion of the first channel region, wherein the first channel region comprises a light sensing area between the first and second end portions of the first channel region;

a first capacitor directly coupled to the first source/drain region of the first transistor;

a second transistor with a second channel region, a third source/drain region disposed on a first end of the second channel region, a fourth source/drain region disposed on a second end of the second channel region, wherein the second channel region comprises a middle portion between the first and second end portions of the second channel region;

a second capacitor directly coupled to the third source/drain region of the second transistor;

a capping material over the middle portion of the second channel region; and

a comparator device electrically coupled to the first source/drain region of the first transistor and the third source/drain region of the second transistor and configured to detect a current difference between the first and second transistors in response to the first transistor being exposed to light.

2. The circuit of claim 1 , wherein the first transistor comprises a first gate terminal and the second transistor comprises a second gate terminal, and wherein the first and second gate terminals are electrically coupled to a voltage source.

3. The circuit of claim 2 , wherein the voltage source comprises a ground voltage source or a negative voltage source.

4. The circuit of claim 1 , wherein the second source/drain region of the first transistor and the fourth source/drain region of the second transistor are electrically coupled to a voltage source.

5. The circuit of claim 4 , wherein the voltage source comprises a ground voltage source or a positive voltage source.

6. The circuit of claim 1 , wherein the first and second transistors are thin film transistors.

7. The circuit of claim 1 , wherein the capping material comprises selenium or selenium oxide.

8. The circuit of claim 1 , further comprising:

a third transistor with a third channel region, a fifth source/drain region, and a sixth source/drain region; and

a fourth transistor with a fourth channel region, a seventh source/drain region, and an eighth source/drain region, wherein:

the sixth source/drain region of the third transistor is electrically coupled to the first source/drain region of the first transistor; and

the eighth source/drain region of the fourth transistor is electrically coupled to the third source/drain region of the second transistor.

9. The circuit of claim 8 , wherein:

the first capacitor comprises first and second terminals, and wherein the first terminal is electrically coupled to the first and sixth source/drain regions of the first and third transistors, respectively, and wherein the second terminal is electrically coupled to a ground voltage source; and

the second capacitor comprises third and fourth terminals, and wherein the third terminal is electrically coupled to the third and eighth source/drain regions of the second and fourth transistors, respectively, and wherein the fourth terminal is electrically coupled to the ground voltage source.

10. The circuit of claim 9 , wherein the first, second, third, and fourth transistors comprise first, second, third, and fourth gate terminals, respectively, wherein:

the first and second gate terminals are electrically coupled to a ground voltage source or a negative voltage source, and

the third gate terminal, fourth gate terminal, the fifth source/drain region of the third transistor, and seventh source/drain region of the fourth transistor are electrically coupled to a positive voltage source.

11. The circuit of claim 8 , wherein the first and second transistors are thin film transistors, and wherein the third and fourth transistors are p-channel complementary metal oxide semiconductor transistors.

12. An integrated circuit structure, comprising:

a device layer, comprising

a comparator device formed on a substrate; and

a thin film transistor device layer disposed on the device layer, wherein the thin film transistor device layer comprises:

a first thin film transistor that comprises a first channel region, a first source/drain region disposed on a first end portion of the first channel region, and a second source/drain region disposed on a second end portion of the first channel region, and wherein the first channel region comprises a light-receiving area between the first and second end portions of the first channel region;

a first capacitor directly coupled to the first source/drain region of the first thin film transistor;

a second thin film transistor that comprises a second channel region, a third source/drain region disposed on a first end of the second channel region, a fourth source/drain region disposed on a second end of the second channel region, and wherein the second channel region comprises a middle portion between the first and second end portions of the second channel region;

a second capacitor directly coupled to the third source/drain region of the second thin film transistor;

a capping material over the middle portion of the second channel region; and

an interconnect structure arranged to electrically couple the first and second thin film transistors to the comparator device.

13. The integrated circuit structure of claim 12 , wherein the first thin film transistor comprises a first gate terminal and the second thin film transistor comprises a second gate terminal, and wherein the first and second gate terminals are electrically coupled to a ground voltage source or a negative voltage source.

14. The integrated circuit structure of claim 12 , wherein the capping material comprises selenium or selenium oxide.

15. The integrated circuit structure of claim 12 , wherein the device layer further comprises:

a first p-channel complementary metal oxide semiconductor transistor with a third channel region, a fifth source/drain region, and a sixth source/drain region; and

a second p-channel complementary metal oxide semiconductor transistor with a fourth channel region, a seventh source/drain region, and an eighth source/drain region, wherein:

the sixth source/drain region of the first p-channel complementary metal oxide semiconductor transistor is electrically coupled to the first source/drain region of the first thin film transistor; and

the eighth source/drain region of the second p-channel complementary metal oxide semiconductor transistor is electrically coupled to the third source/drain region of the second thin film transistor; wherein:

the first capacitor comprises first and second terminals, wherein the first terminal is electrically coupled to the first and sixth source/drain regions of the first thin film transistor and first p-channel complementary metal oxide semiconductor transistor, respectively, and wherein the second terminal is electrically coupled to a ground voltage source; and

the second capacitor comprises third and fourth terminals, wherein the third terminal is electrically coupled to the third and eighth source/drain regions of the second thin film transistor and second p-channel complementary metal oxide semiconductor transistor, respectively, and wherein the fourth terminal is electrically coupled to the ground voltage source.

16. The integrated circuit structure of claim 15 , wherein the fifth source/drain region of the first p-channel complementary metal oxide semiconductor transistor and the seventh source/drain region of the second p-channel complementary metal oxide semiconductor transistor are electrically coupled to a positive voltage source.

17. A circuit, comprising:

a first transistor comprising a first channel region with a light sensing area;

a first capacitor directly coupled to the first transistor;

a second transistor with a second channel region;

a second capacitor directly coupled to the second transistor;

a capping material over the second channel region; and

a comparator device electrically coupled to the first and second transistors and configured to detect a current difference between the first and second transistors in response to the first transistor being exposed to light.

18. The circuit of claim 17 , wherein the first transistor comprises a first gate terminal and the second transistor comprises a second gate terminal, and wherein the first and second gate terminals are electrically coupled to a voltage source.

19. The circuit of claim 18 , wherein the voltage source comprises a ground voltage source or a negative voltage source.

20. The circuit of claim 17 , wherein the capping material comprises selenium or selenium oxide.