IP Library › Granted Patent US 12,333,421
Granted Patent B2
US 12,333,421 · App. 17/461,590 · Granted Jun 17, 2025

Synaptic circuit and neural networking apparatus

Inventors: Kumiko Nomura (Tokyo, JP); Yoshifumi Nishi (Yokohama Kanagawa, JP); Takao Marukame (Tokyo, JP); Koichi Mizushima (Kamakura Kanagawa, JP)
Assignee: Kabushiki Kaisha Toshiba
G06N3/065G06N3/049G06N3/08
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Quick Facts
Patent No.
US 12,333,421
App. No.
17/461,590
Granted
Jun 17, 2025
Kind
B2
Abstract

A synaptic circuit according to an embodiment is a circuit in which a weight value changed by learning is set. The synaptic circuit receives a binary input signal from a pre-synaptic neuron circuit and outputs an output signal to a post-synaptic neuron circuit. The synaptic circuit includes a propagation circuit and a control circuit. The propagation circuit supplies, to the post-synaptic neuron circuit, the output signal obtained by adding an influence of the weight value to the input signal. The control circuit stops output of the output signal from the propagation circuit to the post-synaptic neuron circuit when the weight value is smaller than a predetermined reference value.

Claims (59)

1. A synaptic circuit in which a weight value changed by learning is set, the synaptic circuit receiving a binary input signal indicative of a first value or a second value from a pre-synaptic neuron circuit and outputting an output signal to a post-synaptic neuron circuit, the post-synaptic neuron circuit configured to output a binary firing signal, the synaptic circuit comprising:

a learning circuit configured to update the weight value by spike-timing-dependent synaptic plasticity learning based on the input signal and the firing signal;

a propagation circuit configured to supply, to the post-synaptic neuron circuit, either the output signal represented by an analog value corresponding to the weight value or the output signal obtained by delaying the input signal a time corresponding to the weight value, when the input signal changes from the second value to the first value; and

a control circuit configured to stop output of the output signal from the propagation circuit to the post-synaptic neuron circuit when the weight value is smaller than a predetermined reference value.

2. The synaptic circuit according to claim 1 , wherein the propagation circuit shortens a delay time between reception of the input signal and output of the output signal as the weight values is larger.

3. The synaptic circuit according to claim 1 , further comprising a switch circuit configured to receive the input signal from the pre-synaptic neuron circuit and switch whether or not to give the input signal to the propagation circuit,

wherein the control circuit

turns on the switch circuit to give the input signal to the propagation circuit when the weight value is equal to or larger than the reference value, and

turns off the switch circuit not to give the input signal to the propagation circuit when the weight value is smaller than the reference value.

4. The synaptic circuit according to claim 3 , further comprising a weight holding circuit configured to generate a weight voltage corresponding to the weight value,

wherein the control circuit

receives a reference value voltage corresponding to the reference value and compares the reference value voltage with the weight voltage,

turns on the switch circuit to give the input signal to the propagation circuit when the weight voltage is equal to or higher than the reference value voltage, and

turns off the switch circuit not to give the input signal to the propagation circuit when the weight voltage is smaller than the reference value voltage.

5. The synaptic circuit according to claim 1 , wherein the propagation circuit includes:

a weight current circuit configured to cause, to flow, a weight current having a current value corresponding to the weight value;

an input circuit configured to switch, based on the input signal, whether or not to cause the weight current to flow by the weight current circuit;

a capacitor including a first terminal and a second terminal, the first terminal being given a constant voltage;

an output circuit configured to output the output signal corresponding to a capacitor voltage generated at the second terminal; and

a charge adjustment circuit configured to, when the weight current is flowed by the switching of the input circuit, decrease or increase charges accumulated in the capacitor by

drawing, from the second terminal, a capacitor current corresponding to a current value of the weight current, or

supplying the capacitor current to the second terminal.

6. The synaptic circuit according to claim 1 , further comprising a change circuit configured to change the reference value by:

decreasing the reference value in a stepwise manner with a lapse of time with a preset lower limit reference value as a lower limit when the weight value is smaller than the reference value; and

increasing the reference value in a stepwise manner with a lapse of time with an upper limit reference value larger than the lower limit reference value as an upper limit when the weight value is equal to or larger than the reference value.

7. The synaptic circuit according to claim 1 , further comprising a change circuit configured to

change the reference value to a lower limit reference value after a preset time elapses since timing at which the weight value becomes smaller than the reference value, and

change the reference value to an upper limit reference value larger than the lower limit reference value after a preset time elapses since timing at which the weight value becomes equal to or larger than the reference value.

8. A neural network apparatus comprising:

the synaptic circuit according to claim 1 .

9. The neural network apparatus according to claim 8 , further comprising a recursive structure in which a signal output from a first layer in a plurality of layers is fed back to the first layer or to a layer arranged in a stage before the first layer.

10. The synaptic circuit according to claim 1 , wherein the weight value is represented by Equation (1):

W ij ( t+Δt )= W ij ( t )+Δ W ij ( t )  (1)

where

Δt denotes a unit time,

t denotes a time,

(t+Δt) denotes a time after the unit time Δt has elapsed from the time t,

W ij (t) represents the weight value at the time (t), and

W ij (t+tΔ) represents the weight value at the time t+Δt, and the learning circuit updates the weight value in accordance with Equation (2):

Δ W ij ( t )=η STDP ( x i ( t )× x j ( t−Δt )− x i ( t−Δt )× x j ( t ))  (2)

Where

(t−Δt) denotes a time before the unit time Δt from the time t,

η STDP denotes a predetermined constant,

x i (t) denotes 0 or 1, denoting a value of the firing signal at the time t,

x j (t) denotes 0 or 1, denoting a value of the input signal at the time t,

x i (t−Δt) denotes 0 or 1, denoting a value of the firing signal at the time t−Δt, and

x j (t−Δt) denotes 0 or 1, denoting a value of the input signal at the time t−Δt.

11. A signal processing method, comprising:

by a circuit, performing signal processing in accordance with a neural network, wherein

the neural network comprises:

a first neuron configured to output a binary input signal indicative of a first value or a second value,

a synapse to which a weight value changed by learning is set, and

a second neuron configured to acquire an output signal from the synapse and output a binary firing signal; and

the method comprises:

by the circuit, updating the weight value by spike-timing-dependent synaptic plasticity learning based on the input signal and the firing signal;

when the weight value is equal to larger than a predetermined reference value,

propagating, by the circuit, either the output signal represented by an analog value corresponding to the weight value or the output signal obtained by delaying the input signal a time corresponding to the weight value from the synapse to the first neuron, when the input signal changes from the second value to the first value; and

when the weight value is smaller than the predetermined reference value,

stopping, by the circuit, propagating of the output signal from the synapse to the second neuron.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2021
From: NOMURA, KUMIKO; NISHI, YOSHIFUMI; MARUKAME, TAKAO; MIZUSHIMA, KOICHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 057631/0056 →
Priority Claims (1)
JP 2021-027592 · Feb 24, 2021 · national
Continuity (1)
Related Publication 20220269932A1 · Aug 25, 2022
References Cited (4)
US 20130132314A1 · Snider · 2013 [cited by examiner]
US 20160034812A1 · Gibson · 2016 [cited by examiner]
Zhang, Malu, et al. “Supervised learning in spiking neural networks with synaptic delay-weight plasticity.” Neurocomputing 409 (2020): 103-118. (Year: 2020). [cited by examiner]
Elisabetta Chicca et al., “Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems,” Proc. of the IEEE, vol. 102, No. 9, pp. 1367-1388 (2014). [cited by applicant]