Controllable pattern clustering for characterized semiconductor layout designs
A computing system implementing a physical verification tool can determine principal feature components describing geometric patterns around points of interest in a semiconductor layout design. The principal feature components include topological features indicating whether structures are present around the points of interest, and include dimensional features corresponding to measurements associated with the structures present around the points of interest. The physical verification tool can generate a topological signature for each of the points of interest based on the topological features, and cluster the points of interest into different subsets based on the topological signature. The physical verification tool can perform design rule check operations on the semiconductor layout design to identify whether one or more of the points of interest correspond to a design rule violation and perform pattern matching to identify whether other points of interest match the point of interest corresponding to the design rule violation.
1. A method comprising:
determining, by a computing system, principal feature components that describe geometric patterns around points of interest in a semiconductor layout design, wherein the principal feature components include a plurality of topological features for each of the points of interest in the semiconductor layout design, which indicate whether structures are present in different directions around the points of interest, wherein the principal feature components include a plurality of dimensional features for each of the points of interest in the semiconductor layout design, which correspond to measurements associated with the points of interest or the structures present around the points of interest;
generating, by the computing system, a topological signature for each of the points of interest in the semiconductor layout design based on the topological features in the principal feature components;
selecting, by the computing system, one or more of the dimensional features for each of the points of interest in the semiconductor layout design, wherein the selection corresponds to a level of granularity to cluster the points of interest;
performing, by the computing system, topological clustering for the points of interest, which groups the points of interest into subsets based, at least in part, on the topological signature; and
refining, by the computing system, the topological clustering of the points of interest by clustering the points of interest into different subsets based, at least in part, on the selected dimensional features.
2. The method of claim 1 , wherein the dimensional features include ordinal angles between the different directions around the points of interest corresponding to the topological features.
3. The method of claim 1 , wherein the dimensional features include hypotenuse distances corresponding to distances between the points of interest and the structures that the topological features indicate were present around the points of interest.
4. The method of claim 1 , further comprising:
performing, by the computing system, design rule check operations on the semiconductor layout design to identify whether one or more of the points of interest correspond to a design rule violation; and
performing, by the computing system, pattern matching to identify whether any of the points of interest match the one or more of the points of interest corresponding to the design rule violation based, at least in part, on the dimensional features.
5. The method of claim 4 , wherein the pattern matching identifies which of the dimensional features corresponds to the design rule violation.
6. The method of claim 1 , wherein the points of interest comprises edges in the semiconductor layout design.
7. A system comprising:
a memory system configured to store computer-executable instructions; and
a computing system, in response to execution of the computer-executable instructions, is configured to:
determine principal feature components that describe geometric patterns around points of interest in a semiconductor layout design, wherein the principal feature components include a plurality of topological features for each of the points of interest in the semiconductor layout design, which indicate whether structures are present in different directions around the points of interest, wherein the principal feature components include a plurality of dimensional features for each of the points of interest in the semiconductor layout design, which correspond to measurements associated with the points of interest or the structures present around the points of interest;
generate a topological signature for each of the points of interest in the semiconductor layout design based on the topological features in the principal feature components;
select one or more of the dimensional features for each of the points of interest in the semiconductor layout design, wherein the selection corresponds to a level of granularity to cluster the points of interest;
perform topological clustering for the points of interest, which groups the points of interest into subsets based, at least in part, on the topological signature; and
refine the topological clustering of the points of interest by clustering the points of interest into different subsets based, at least in part, on the selected dimensional features.
8. The system of claim 7 , wherein the dimensional features include ordinal angles between the different directions around the points of interest corresponding to the topological features.
9. The system of claim 7 , wherein the dimensional features include hypotenuse distances corresponding to distances between the points of interest and the structures that the topological features indicate were present around the points of interest.
10. The system of claim 7 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:
perform design rule check operations on the semiconductor layout design to identify whether one or more of the points of interest correspond to a design rule violation; and
perform pattern matching to identify whether any of the points of interest match the one or more of the points of interest corresponding to the design rule violation based, at least in part, on the dimensional features.
11. The system of claim 10 , wherein the pattern matching identifies which of the dimensional features corresponds to the design rule violation.
12. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
determining principal feature components that describe geometric patterns around points of interest in a semiconductor layout design, wherein the principal feature components include a plurality of topological features for each of the points of interest in the semiconductor layout design, which indicate whether structures are present in different directions around the points of interest, wherein the principal feature components include a plurality of dimensional features for each of the points of interest in the semiconductor layout design, which correspond to measurements associated with the points of interest or the structures present around the points of interest;
generating a topological signature for each of the points of interest in the semiconductor layout design based on the topological features in the principal feature components;
selecting one or more of the dimensional features for each of the points of interest in the semiconductor layout design, wherein the selection corresponds to a level of granularity to cluster the points of interest;
performing topological clustering for the points of interest, which groups the points of interest into subsets based, at least in part, on the topological signature; and
refining the topological clustering of the points of interest by clustering the points of interest into different subsets based, at least in part, on the selected dimensional features.
13. The apparatus of claim 12 , wherein the dimensional features include ordinal angles between the different directions around the points of interest corresponding to the topological features.
14. The apparatus of claim 12 , wherein the dimensional features include hypotenuse distances corresponding to distances between the points of interest and the structures that the topological features indicate were present around the points of interest.
15. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:
performing design rule check operations on the semiconductor layout design to identify whether one or more of the points of interest correspond to a design rule violation; and
performing pattern matching to identify whether any of the points of interest match the one or more of the points of interest corresponding to the design rule violation based, at least in part, on the dimensional features.
16. The apparatus of claim 15 , wherein the pattern matching identifies which of the dimensional features corresponds to the design rule violation.
17. The apparatus of claim 12 , wherein the points of interest comprises edges in the semiconductor layout design.