State dependent and path dependent power estimation

1. A method comprising:

detecting, by a computing system, toggles of signals in waveform data generated during functional verification of a circuit design describing an electronic device;

correlating, by the computing system, the toggles in the signals of the waveform data to one of a plurality of arcs associated with the logic gates in the circuit design;

tracking, by the computing system, a number of times each of the arcs associated with logic gates has been correlated to the detected toggles;

determining, by the computing system, power estimates for each arc of the logic gates based, at least in part, on the tracked number of times each of the arcs associated with logic gates has been correlated to the detected toggles; and

generating, by the computing system, an estimate of power consumption for the circuit design during the functional verification by accumulating the power estimates for the arcs associated with the logic gates.

2. The method of claim 1 , wherein determining the power estimates for each arc of the logic gates further comprises:

identifying an input capacitance to edges of the logic gates and slews corresponding to electrical transition times for each arc in the logic gates of the circuit design; and

retrieving energy values for each arc from an energy table described in a technology file that is indexed with a combination of the input capacitances and the slews, wherein the power estimates for each arc of the logic gates are determined based on the energy values.

3. The method of claim 2 , wherein determining the power estimates for each of the arc of the logic gates further comprises multiplying the retrieved energy values by the tracked number of times each of the arcs associated with logic gates has been correlated to the detected toggles.

4. The method of claim 1 , further comprising reading, by the computing system, the waveform data for all of the logic gates with a time-based iterator.

5. The method of claim 1 , wherein correlating the toggles in the signals of the waveform data to one of the arcs associated with the logic gates in the circuit design further comprises:

mapping edges of the logic gates in the circuit design corresponding to at least one of the arcs to signals in the waveform data; and

determining the detected toggles in the signals correlate to the edges of the logic gates in the circuit design corresponding to at least one of the arcs based on the mapping.

6. The method of claim 1 , further comprising generating, by the computing system, compiled code that, when called in response to the toggles in the signals of the waveform data, is configured to dynamically generate shared objects that correlate the toggles in the signals of the waveform data to one of the arcs associated with the logic gates in the circuit design and track the number of times each of the arcs associated with logic gates has been correlated to the detected toggles.

7. The method of claim 1 , further comprising performing the functional verification of the circuit design to generate the waveform data.

8. A system comprising:

a memory system configured to store computer-executable instructions; and

a computing system, in response to execution of the computer-executable instructions, is configured to:

detect toggles of signals in waveform data generated during functional verification of a circuit design describing an electronic device;

correlate the toggles in the signals of the waveform data to one of a plurality of arcs associated with the logic gates in the circuit design;

track a number of times each of the arcs associated with logic gates has been correlated to the detected toggles;

determine power estimates for each arc of the logic gates based, at least in part, on the tracked number of times each of the arcs associated with logic gates has been correlated to the detected toggles; and

generate an estimate of power consumption for the circuit design during the functional verification by accumulating the power estimates for the arcs associated with the logic gates.

9. The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the power estimates for each of the arc of the logic gates by:

identifying an input capacitance to edges of the logic gates and slews corresponding to electrical transition times for each arc in the logic gates of the circuit design; and

retrieving energy values for each arc from an energy table described in a technology file that is indexed with a combination of the input capacitances and the slews, wherein the power estimates for each arc of the logic gates are determined based on the energy values.

10. The system of claim 9 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the power estimates for each of the arc of the logic gates by multiplying the retrieved energy values by the tracked number of times each of the arcs associated with logic gates has been correlated to the detected toggles.

11. The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to read the waveform data for all of the logic gates with a time-based iterator.

12. The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to correlate the toggles in the signals of the waveform data to one of the arcs associated with the logic gates in the circuit design by:

mapping edges of the logic gates in the circuit design corresponding to at least one of the arcs to signals in the waveform data; and

determining the detected toggles in the signals correlate to the edges of the logic gates in the circuit design corresponding to at least one of the arcs based on the mapping.

13. The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to generate compiled code that, when called in response to the toggles in the signals of the waveform data, is configured to dynamically generate shared objects that correlate the toggles in the signals of the waveform data to one of the arcs associated with the logic gates in the circuit design and track the number of times each of the arcs associated with logic gates has been correlated to the detected toggles.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

detecting toggles of signals in waveform data generated during functional verification of a circuit design describing an electronic device;

correlating the toggles in the signals of the waveform data to one of a plurality of arcs associated with the logic gates in the circuit design;

tracking a number of times each of the arcs associated with logic gates has been correlated to the detected toggles;

determining power estimates for each arc of the logic gates based, at least in part, on the tracked number of times each of the arcs associated with logic gates has been correlated to the detected toggles; and

generating an estimate of power consumption for the circuit design during the functional verification by accumulating the power estimates for the arcs associated with the logic gates.

15. The apparatus of claim 14 , wherein determining the power estimates for each arc of the logic gates further comprises:

identifying an input capacitance to edges of the logic gates and slews corresponding to electrical transition times for each arc in the logic gates of the circuit design; and

retrieving energy values for each arc from an energy table described in a technology file that is indexed with a combination of the input capacitances and the slews, wherein the power estimates for each arc of the logic gates are determined based on the energy values.

16. The apparatus of claim 15 , wherein determining the power estimates for each of the arc of the logic gates further comprises multiplying the retrieved energy values by the tracked number of times each of the arcs associated with logic gates has been correlated to the detected toggles.

17. The apparatus of claim 14 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising reading the waveform data for all of the logic gates with a time-based iterator.

18. The apparatus of claim 14 , wherein correlating the toggles in the signals of the waveform data to one of the arcs associated with the logic gates in the circuit design further comprises:

mapping edges of the logic gates in the circuit design corresponding to at least one of the arcs to signals in the waveform data; and

determining the detected toggles in the signals correlate to the edges of the logic gates in the circuit design corresponding to at least one of the arcs based on the mapping.

19. The apparatus of claim 14 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising generating compiled code that, when called in response to the toggles in the signals of the waveform data, is configured to dynamically generate shared objects that correlate the toggles in the signals of the waveform data to one of the arcs associated with the logic gates in the circuit design and track the number of times each of the arcs associated with logic gates has been correlated to the detected toggles.

20. The apparatus of claim 14 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising performing the functional verification of the circuit design to generate the waveform data.