Integrated circuit device and method
An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
1. An integrated circuit (IC) device, comprising:
a substrate; and
a first cell and a second cell over the substrate, the first cell adjacent the second cell, each of the first cell and the second cell comprising at least one active region and at least one gate region extending across the at least one active region,
wherein
the first cell comprises a first input/output (TO) pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis transverse to the first axis,
the second cell comprises a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern, and
the first metal layer further comprises a first connecting pattern along the first track and connecting the first IO pattern of the first cell and a second IO pattern of the second cell, wherein the second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
2. The IC device of claim 1 , wherein
the plurality of conductive patterns of the second cell comprises multiple IO patterns of the second cell electrically coupled with each other.
3. The IC device of claim 1 , wherein
each of the first cell and the second cell further comprises conductive patterns in the first metal layer and a second metal layer,
one of the first metal layer and the second metal layer corresponds to a front side metal layer of the IC device, and the other of the first metal layer and the second metal layer corresponds to a back side metal layer of the IC device, and
the second cell has at least one further conductive pattern along at least one corresponding track in the second metal layer, the further conductive pattern being an IO pattern of the second cell or a floating conductive pattern.
4. The IC device of claim 1 , wherein
the first cell further comprises a third IO pattern along a second track among the plurality of tracks,
the first IO pattern and the third IO pattern are configured to receive data which are swappable with each other without changing a function configured to be performed by the first cell, and
one of the plurality of conductive patterns of the second cell is along the second track.
5. The IC device of claim 1 , wherein
the plurality of conductive patterns of the second cell further comprises
a third IO pattern of the second cell along a second track among the plurality of tracks, and
a first floating conductive pattern along a third track among the plurality of tracks, and
the IC device further comprises:
a second connecting pattern in a second metal layer, and
vias electrically coupling the second connecting pattern correspondingly to the second IO pattern and the third IO pattern.
6. The IC device of claim 1 , wherein
the plurality of conductive patterns of the second cell further comprises
a third IO pattern of the second cell along a second track among the plurality of tracks, and
a first floating conductive pattern along a third track among the plurality of tracks,
the IC device further comprises:
an extended contact structure over and in electrical contact with the at least one active region in the second cell, and
vias electrically coupling the extended contact structure correspondingly to the second IO pattern and the third IO pattern, and
the extended contact structure overlaps, without being electrically coupled to, the first floating conductive pattern.
7. The IC device of claim 1 , further comprising a second metal layer, wherein
one of the first metal layer and the second metal layer corresponds to a front side metal layer of the IC device, and the other of the first metal layer and the second metal layer corresponds to a back side metal layer of the IC device,
the second cell has a third IO pattern along a corresponding track in the second metal layer,
the IC device further comprises:
an extended contact structure over and in electrical contact with the at least one active region in the second cell,
vias electrically coupling the extended contact structure correspondingly to the second IO pattern in the first metal layer and the third IO pattern in the second metal layer, and
the extended contact structure overlaps, without being electrically coupled to, a floating conductive pattern among the plurality of conductive patterns of the second cell.
8. A method, comprising:
generating a layout diagram of an integrated circuit (IC) device; and
manufacturing the IC device based on the generated layout diagram,
wherein
said generating the layout diagram comprises:
placing a first cell adjacent a second cell in the layout diagram, each of the first cell and the second cell comprising at least one active region and at least one gate region extending across the at least one active region, wherein the first cell comprises a first input/output (TO) pattern, the second cell comprises a second IO pattern corresponding to the first IO pattern, and the first IO pattern and the second IO pattern are in a first metal layer and aligned along a first axis; and
routing, in the first metal layer, a connecting pattern between the first IO pattern and the second IO pattern, wherein the connecting pattern is contiguous to, and aligned along the first axis with, both of the first IO pattern and the second IO pattern, and
the first metal layer is a metal-zero (M0) layer or a back-side-metal-zero (M0_B) layer.
9. The method of claim 8 , wherein
said placing comprises placing a first boundary of the first cell in abutment with a second boundary of the second cell.
10. The method of claim 8 , wherein
said placing comprises placing a first boundary of the first cell at a space along the first axis from a second boundary of the second cell, and
the space is unfilled by a non-filler cell.
11. The method of claim 8 , further comprising:
before said placing, selecting the second cell from a plurality of cells,
wherein
the plurality of cells has same circuitry, and corresponding IO patterns along corresponding different tracks among a plurality of tracks in the first metal layer,
the plurality of tracks is spaced from each other along a second axis transverse to the first axis,
the first IO pattern of the first cell is along a first track among the plurality of tracks, and
said selecting comprises selecting, from the plurality of cells, the second cell having the corresponding second IO pattern along the first track.
12. The method of claim 11 , further comprising:
before said placing, transforming the second cell by performing at least one of
flipping the second cell across the second axis, or
switching positions of conductive patterns of the second cell in the first metal layer and conductive patterns of the second cell in a second metal layer with each other, one of the first metal layer and the second metal layer corresponding to a front side metal layer of the IC device, and the other of the first metal layer and the second metal layer corresponding to a back side metal layer of the IC device.
13. The method of claim 12 , wherein
the first metal layer is the M0 layer, and the second metal layer is a metal-one (M1) layer, or
the first metal layer is the M0_B layer, and the second metal layer is a back-side-metal-one (M1_B) layer.
14. The method of claim 8 , wherein
the second cell comprises a plurality of IO patterns electrically coupled with each other and arranged along corresponding different tracks among a plurality of tracks in the first metal layer,
the plurality of tracks is spaced from each other along a second axis transverse to the first axis,
the first IO pattern of the first cell is along a first track among the plurality of tracks, and
the second IO pattern being routed by the connecting pattern to the first IO pattern is one of the plurality of IO patterns and is along the first track.
15. The method of claim 14 , wherein
said routing further comprises generating at least one of a via or a conductive pattern in a second metal layer to electrically couple the second IO pattern with a further IO pattern among the plurality of IO patterns.
16. The method of claim 11 , wherein
the first cell further comprises a third IO pattern along a second track among the plurality of tracks,
the first IO pattern and the third IO pattern are configured to receive data which are swappable with each other without changing a function configured to be performed by the first cell, and
said selecting the second cell is performed in response to a determination that none of the plurality of cells has the corresponding IO pattern along the second track.
17. The method of claim 11 , further comprising:
before said placing, flipping the second cell across the second axis, to rearrange the second IO pattern from a first side to a second side opposite the first side along the first axis, the second side facing the first cell along the first axis.
18. The method of claim 11 , wherein
each of the first cell and the plurality of cells comprises conductive patterns in the first metal layer and a second metal layer,
one of the first metal layer and the second metal layer corresponds to a front side metal layer of the IC device, and the other of the first metal layer and the second metal layer corresponds to a back side metal layer of the IC device, and
the second cell selected from the plurality of cells has the corresponding IO pattern along a track in the second metal layer.
19. The method of claim 18 , further comprising:
before said placing, switching positions of conductive patterns of the second cell in the first metal layer and conductive patterns of the second cell in the second metal layer with each other.
20. A method, comprising:
generating a layout diagram of an integrated circuit (IC) device; and
manufacturing the IC device based on the generated layout diagram,
wherein
said generating the layout diagram comprises:
placing a first cell adjacent a second cell in the layout diagram, each of the first cell and the second cell comprising at least one active region and at least one gate region extending across the at least one active region, wherein the first cell comprises a first input/output (TO) pattern, the second cell comprises a second IO pattern corresponding to the first IO pattern, and the first IO pattern and the second IO pattern are in a first metal layer and aligned along a first axis; and
routing, in the first metal layer, a connecting pattern between the first IO pattern and the second IO pattern, wherein the connecting pattern is contiguous to, and aligned along the first axis with, both of the first IO pattern and the second IO pattern, and
said generating the layout diagram further comprises, before said placing, transforming the second cell by performing at least one of:
flipping the second cell across a second axis transverse to the first axis, or
switching positions of conductive patterns of the second cell in the first metal layer and conductive patterns of the second cell in a second metal layer with each other, one of the first metal layer and the second metal layer corresponding to a front side metal layer of the IC device, and the other of the first metal layer and the second metal layer corresponding to a back side metal layer of the IC device.