Stacked complementary field effect transistors
A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.
1. A CFET structure (complementary field effect transistor) comprising:
a first transistor disposed above a second transistor; and
a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a sacrificial spacer layer disposed in contact with the second source drain region, the sacrificial spacer layer comprising an upper surface at a height of an uppermost portion of the second source/drain region, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region, a surface of the recessed notch disposed at a height below the upper surface of the sacrificial spacer layer.
2. The CFET structure according to claim 1 , further comprising a first dielectric material disposed in the notch and in contact with a bottom surface of the first source-drain region.
3. The CFET structure according to claim 1 , further comprising a metal contact disposed in contact with the first source/drain region.
4. The CFET structure according to claim 1 , further comprising a second metal contact disposed in contact with the second source/drain region.
5. The CFET structure according to claim 1 , further comprising a metal gate structure disposed adjacent to the first source/drain region and the second source drain region.
6. The CFET structure according to claim 1 , wherein the first transistor comprises an nFET.
7. The CFET structure according to claim 1 , wherein the first transistor comprises a pFET.