Memory dice internal clock

1. A method, comprising:

selecting a primary ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device;

setting the primary R/B # pin to low status;

receiving, by at least one memory die among the plurality of memory dice, signaling indicative of performance of a memory access for the primary R/B # pin;

receiving, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a first memory die among the plurality of memory dice;

receiving, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a second memory die among the plurality of memory dice;

initiating a first internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the first memory die among the plurality of memory dice; and

initiating a second internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the second memory die among the plurality of memory dice, wherein the first internal clocking signal and the second internal clocking signal are associated with timing of operations performed by the plurality of memory dice.

2. The method of claim 1 , wherein selecting, receiving, and initiating are performed as part of a peak power management operation involving the plurality of memory dice.

3. The method of claim 1 , further comprising receiving signaling indicative of the performance of the memory access through a resistor that is resident on the plurality of memory dice.

4. The method of claim 1 , further comprising checking a power status of the primary R/B # pin prior to the performance of the memory access on the plurality of memory dice.

5. The method of claim 1 , further comprising setting the primary R/B # pin to high when the respective memory dice of the plurality of memory dice completes memory access.

6. The method of claim 1 , wherein the plurality of R/B # pins are exclusive of each other.

7. The method of claim 1 , further comprising receiving signaling indicative of the performance of the memory access for the plurality of memory dice independently on different physical channels.

8. The method of claim 1 , further comprising receiving signaling of performance of the memory access for the plurality of R/B # pins after signaling of performance of the memory access for the primary R/B # pin has been received.

9. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:

select a primary ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device;

set the primary R/B # pin to low status;

receive, by at least one memory die among the plurality of memory dice, signaling indicative of performance of memory access for the primary R/B # pin;

receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a first memory die among the plurality of memory dice;

receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a second memory die among the plurality of memory dice;

initiate a first internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the first memory die among the plurality of memory dice; and

initiate a second internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the second memory die among the plurality of memory dice.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the primary R/B # pin is set to low status throughout the performance of the memory access of the plurality of memory dice.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the instructions, when executed, further cause the processor to receive signaling indicative of performance of the memory access of the plurality of memory dice concurrently.

12. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions, when executed, further cause the processor to configure the plurality of memory dice concurrently.

13. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions, when executed, further cause the processor to pause performance of the memory access of the plurality of memory dice associated with the plurality of R/B # pins prior to pausing performance of the memory access of the memory dice associated with the primary R/B # pin having the primary R/B # pin.

14. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions, when executed, further cause the processor to commence performance of the memory access of the plurality of memory dice having the plurality of R/B # pins after commencing performance of the memory access of a memory dice having the primary R/B # pin.

15. The non-transitory computer-readable storage medium of claim 9 , wherein the plurality of R/B # pins consists 4 R/B # pins with a 5 th R/B # pin as the primary R/B # pin.

16. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions, when executed, further cause the processor to simultaneously commence operation of the first memory dice and the second memory dice.

17. A system, comprising:

a plurality of memory components that share a peak power characteristic, wherein each memory component is associated with a ready/busy pin (R/B #) among a plurality of R/B # pins; and

a processor operatively coupled to the plurality of memory components, to:

select a particular R/B # pin from the plurality of R/B # pins to have a singular status for the plurality of memory components;

receive, by at least one memory die among a plurality of memory dice, signaling indicative of performance of a memory access of a first memory component of the plurality of memory components;

receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access of a second memory component of the plurality of memory components responsive to signaling indicative of completion of the performance of the memory access of the first memory component of the plurality of memory components; and

initiate an internal clocking signal subsequent to receipt of the signaling indicative of completion of performance of the memory access of a last memory component of the plurality of memory components.

18. The system of claim 17 , wherein the processor staggers performance of a memory access of the plurality of memory components such that the second memory component of the plurality of memory components commences performance of the memory access at a delayed time as compared to the performance of the memory access of the first memory component of the plurality of memory components.

19. The system of claim 17 , wherein the internal clock signal for the plurality of memory components is initiated only responsive to the particular R/B # pin being set to low.

20. The system of claim 17 , wherein the plurality of memory components comprise a NAND flash memory device.