Display device incuding hole region in display area
A display device includes: a substrate in which a transmission area, a display area, a non-display area and the display area, and a peripheral area are defined; pixels arranged on the display area; initialization gate lines and compensation gate lines extending along pixel rows; gate driving circuits disposed on the peripheral area; and gate connection lines disposed on the non-display area. A k-th gate driving circuit among the gate driving circuits simultaneously drives m-th and (m+1)-th initialization gate lines and n-th and (n+1)-th compensation gate lines. First portions of the n-th and (n+1)-th compensation gate lines and second portions of the n-th and (n+1)-th compensation gate lines, which are physically apart from each other by the transmission area, are electrically connected to each other through a first gate connection line among gate connection lines.
1. A display device comprising:
a substrate in which a transmission area, a display area surrounding at least a portion of the transmission area, a non-display area between the transmission area and the display area, and a peripheral area outside the display area are defined;
a plurality of pixels arranged on the display area in pixel rows and pixel columns;
a plurality of initialization gate lines and a plurality of compensation gate lines respectively extending along the pixel rows;
a plurality of gate driving circuits disposed on the peripheral area and arranged in a direction of the pixel columns; and
a plurality of gate connection lines disposed on the non-display area,
wherein a k-th gate driving circuit among the plurality of gate driving circuits simultaneously drives m-th and (m+1)-th initialization gate lines among the plurality of initialization gate lines and n-th and (n+1)-th compensation gate lines among the plurality of compensation gate lines,
each of the m-th and (m+1)-th initialization gate lines and each of the n-th and (n+1)-th compensation gate lines include a first portion and a second portion which are physically apart from each other by the transmission area, and
the first portion and the second portion of each of the n-th and (n+1)-th compensation gate lines are electrically connected to each other through a first gate connection line among the plurality of gate connection lines,
wherein k and n are a natural number, and
m is a natural number greater than n+1.
2. The display device of claim 1 , wherein an even number of pixel rows are between an (n+1)-th pixel row and an m-th pixel row.
3. The display device of claim 2 , wherein the first portion and the second portion of each of the m-th and (m+1)-th initialization gate lines are electrically connected to each other through a second gate connection line among the plurality of gate connection lines.
4. The display device of claim 2 , wherein the first gate connection line electrically connects the first portion and the second portion of each of the m-th and (m+1)-th initialization gate lines to each other.
5. The display device of claim 1 , wherein
two pixel rows are between an (n+1)-th pixel row and an m-th pixel row,
n-th and (n+1)-th initialization gate lines among the plurality of initialization gate lines are simultaneously driven by a (k−2)-th gate driving circuit among the plurality of gate driving circuits, and
m-th and (m+1)-th compensation gate lines among the plurality of compensation gate lines are simultaneously driven by a (k+2)-th gate driving circuit among the plurality of gate driving circuits.
6. The display device of claim 1 , wherein an m-th pixel row is a pixel row next to an (n+1)-th pixel row.
7. The display device of claim 6 , wherein the first gate connection line electrically connects the first portion and the second portion of each of the m-th and (m+1)-th initialization gate lines to each other.
8. The display device of claim 6 , wherein the first portion and the second portion of each of the m-th and (m+1)-th initialization gate lines are electrically connected to each other through a second gate connection line among the plurality of gate connection lines.
9. The display device of claim 1 , wherein
n-th and (n+1)-th initialization gate lines among the plurality of initialization gate lines are simultaneously driven by a (k−1)-th gate driving circuit among the plurality of gate driving circuits, and
m-th and (m+1)-th compensation gate lines among the plurality of compensation gate lines are simultaneously driven by a (k+1)-th gate driving circuit among the plurality of gate driving circuits.
10. The display device of claim 1 , wherein the m+1 is equal to 2 k.
11. The display device of claim 1 , wherein the k-th gate driving circuit comprises:
a one-side gate driving circuit disposed on one side of the peripheral area, wherein the one-side gate driving circuit outputs a first gate signal to the first portion of each of the m and (m+1)-th initialization gate lines and the first portion of each of the n-th and (n+1)-th compensation gate lines; and
an other-side gate driving circuit disposed on another side of the peripheral area, wherein the other-side gate driving circuit outputs a second gate signal to the second portion of each of the m and (m+1)-th initialization gate lines and the second portion of each of the n-th and (n+1)-th compensation gate lines.
12. The display device of claim 1 , further comprising:
a plurality of scan lines respectively extending along the pixel rows;
a plurality of scan driving circuits disposed on the peripheral area in a column direction, wherein the plurality of scan driving circuits sequentially drives the plurality of scan lines; and
a plurality of scan connection lines disposed on the non-display area,
wherein each of n-th and (n+1)-th scan lines among the plurality of scan lines includes a first portion and a second portion which are physically apart from each other by the transmission area,
the first portion and the second portion of the n-th scan line are electrically connected to each other through a first scan connection line among the plurality of scan connection lines, and
the first portion and the second portion of the (n+1)-th scan line are electrically connected to each other through a second scan connection line among the plurality of scan connection lines.
13. The display device of claim 12 , wherein the first scan connection line comprises:
a first scan connection electrode electrically connecting the first portion of the n-th scan line to the second portion of the n-th scan line; and
a second scan connection electrode electrically connecting the first portion of the n-th scan line to the second portion of the n-th scan line.
14. The display device of claim 13 , further comprising:
a first conductive layer comprising the first scan connection electrode;
a semiconductor layer on the first conductive layer; and
a second conductive layer on the semiconductor layer and comprising the second scan connection electrode.
15. The display device of claim 1 , further comprising:
a plurality of emission control lines respectively extending along the pixel rows; and
a plurality of emission control driving circuits disposed on the peripheral area and arranged in the direction of the pixel columns,
wherein each of n-th and (n+1)-th emission control lines among the plurality of emission control lines includes a first portion and a second portion which are physically apart and electrically insulated from each other by the transmission area,
the first portion of the n-th emission control line and the first portion of the (n+1)-th emission control line are simultaneously driven by a first emission control driving circuit on one side of the peripheral area among the plurality of emission control driving circuits, and
the second portion of the n-th emission control line and the second portion of the (n+1)-th emission control line are simultaneously driven by a second emission control driving circuit on another side of the peripheral area among the plurality of emission control driving circuits.
16. The display device of claim 1 , further comprising:
a plurality of emission control lines respectively extending along the pixel rows;
a plurality of emission control driving circuits disposed on the peripheral area and arranged in the direction of the pixel columns; and
an emission control connection line disposed on the non-display area,
wherein each of n-th and (n+1)-th emission control lines among the plurality of emission control lines includes a first portion and a second portion which are physically apart from each other by the transmission area, and
the first portion and the second portion of each of the n-th and (n+1)-th emission control lines are electrically connected to each other through the emission control connection line.
17. The display device of claim 1 , wherein each of pixels arranged in an n-th pixel row among the plurality of pixels comprises:
a light-emitting element;
a driving transistor which controls a current flowing to the light-emitting element based on a gate-source voltage;
a scan transistor which transmits a data voltage to the driving transistor in response to a scan signal;
a gate initialization transistor which applies an initialization voltage to a gate of the driving transistor in response to a signal transmitted through an n-th initialization gate line among the plurality of initialization gate lines; and
a compensation transistor which connects a drain of the driving transistor to the gate of the driving transistor in response to a signal transmitted through the n-th compensation gate line.
18. The display device of claim 17 , wherein a conductivity type of each of the gate initialization transistor and the compensation transistor is opposite to a conductivity type of the scan transistor.
19. The display device of claim 17 , further comprising:
a first semiconductor layer comprising an active region of the scan transistor;
a second semiconductor layer comprising an active region of the gate initialization transistor and an active region of the compensation transistor; and
a conductive layer between the first semiconductor layer and the second semiconductor layer.
20. The display device of claim 19 , wherein
the first semiconductor layer comprises a silicon semiconductor material, and
the second semiconductor layer comprises an oxide semiconductor material.
21. The display device of claim 17 , wherein an on-duration length of the signal transmitted through the n-th compensation gate line is equal to twice an on-duration length of the scan signal or greater than the on-duration length of the scan signal.
22. The display device of claim 1 , wherein a through hole is defined through the substrate to correspond to the transmission area.
23. A display device comprising:
a substrate in which a transmission area, a display area surrounding at least a portion of the transmission area, a non-display area between the transmission area and the display area, and a peripheral area outside the display area are defined;
a plurality of pixels arranged on the display area in pixel rows and pixel columns;
a plurality of gate lines respectively extending along the pixel rows; and
a plurality of gate connection lines disposed on the non-display area,
each of m-th and (m+1)-th gate lines and n-th and (n+1)-th gate lines includes a first portion and a second portion which are physically apart from each other by the transmission area,
the first portion of each of the m-th, (m+1)-th, n-th, and (n+1)-th gate lines are connected to each other in the peripheral area, and
the first portion and the second portion of each of the m-th and (m+1)-th gate lines are electrically connected to each other through a first gate connection line among the plurality of gate connection lines,
wherein n is a natural number, and
m is a natural number greater than n+1.
24. The display device of claim 23 , wherein the first portion and the second portion of each of the n-th and (n+1)-th gate lines are electrically connected to each other through a second gate connection line among the plurality of gate connection lines.
25. The display device of claim 23 , wherein the first gate connection line electrically connects the first portion and the second portion of each of the n-th and (n+1)-th gate lines to each other.
26. The display device of claim 23 , wherein the second portion of each of the m-th, (m+1)-th, n-th, and (n+1)-th gate lines are connected to each other in the peripheral area.