Non-volatile read refresh operation comprising discharging a plurality of word lines
A memory system includes: a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and a controller configured to control the nonvolatile memory device to perform a read operation on the plurality of memory blocks, wherein the read operation includes: a first operation of supplying a first voltage level to the plurality of word lines, a second operation of discharging the plurality of word lines to a second voltage level, a third operation of supplying a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation of discharging the plurality of word lines to a fourth voltage level.
1 . A memory system comprising:
a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and
a controller configured to control the nonvolatile memory device to perform a read refresh operation on the plurality of memory blocks,
wherein the read refresh operation includes:
a first operation of driving a first voltage level to each of the plurality of word lines,
a second operation of discharging each of the plurality of word lines to a second voltage level,
a third operation of driving a third voltage level less than the first voltage level to each of the plurality of word lines, and
a fourth operation of discharging each of the plurality of word lines to a fourth voltage level,
wherein the first voltage level is a level higher by a set level than a voltage level for turning on a memory cell with a highest threshold voltage level among the plurality of memory cells, and
wherein the third voltage level is a level for turning on some of the plurality of memory cells and turning off the others.
2 . The memory system of claim 1 , wherein each of the second voltage level and the fourth voltage level are a ground voltage level.
3 . The memory system of claim 1 ,
wherein each of the plurality of memory blocks further includes a first select line and a second select line, the plurality of word lines being arranged between the first select line and the second select line, and
wherein the read refresh operation further includes:
substantially maintaining the first and second select lines to a turn-on voltage level during the first operation or the third operation,
substantially maintaining the first and second select lines to one of the turn-on voltage level and a turn-off voltage level during the second operation, and
substantially maintaining the first and second select lines to the turn-off voltage level during the fourth operation.
4 . The memory system of claim 1 , wherein the controller is further configured to determine when to start the read refresh operation on the basis of a number of accesses to the plurality of memory blocks.
5 . The memory system of claim 4 , wherein the controller is further configured to select, as a target memory block for the read refresh operation, one of the memory blocks based on timings of most recent accesses to the memory blocks.
6 . The memory system of claim 1 ,
wherein the plurality of memory blocks are divided into first and second block groups, within each of which the memory blocks share a bit line, and
wherein the controller is further configured to determine:
when to start the read refresh operation on a memory block within the first block group on the basis of a number of accesses to the first block group, and
when to start the read refresh operation on a memory block within the second block group on the basis of a number of accesses to the second block group.
7 . The memory system of claim 6 ,
wherein the controller is further configured to select, as a target memory block for the read refresh operation, a memory block within the first block group based on timings of most recent accesses to the memory blocks within the first block group, and
wherein the controller is further configured to select, as a target memory block for the read refresh operation, a memory block within the second block group based on timings of most recent accesses to the memory blocks within the second block group.
8 . A nonvolatile memory device comprising:
a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and
a control circuit configured to perform a read refresh operation on a selected memory block among the plurality of memory blocks,
wherein the read refresh operation includes:
a first operation of driving a first voltage level to each of the plurality of word lines,
a second operation of discharging each of the plurality of word lines to a second voltage level,
a third operation of driving a third voltage level less than the first voltage level to each of the plurality of word lines, and
a fourth operation of discharging each of the plurality of word lines to a fourth voltage level,
wherein the first voltage level is a level higher by a set level than a voltage level for turning on a memory cell with a highest threshold voltage level among the plurality of memory cells, and
wherein the third voltage level is a level for turning on some of the plurality of memory cells and turning off the others.
9 . The nonvolatile memory device of claim 8 , wherein each of the second voltage level and the fourth voltage level is a ground voltage level.
10 . The nonvolatile memory device of claim 8 ,
wherein each of the plurality of memory blocks further includes a first select line and a second select line, the plurality of word lines being arranged between the first select line and the second select line, and
wherein the read refresh operation further includes:
substantially maintaining the first and second select lines to a turn-on voltage level during the first operation or the third operation,
substantially maintaining the first and second select lines to one of the turn-on voltage level and a turn-off voltage level during the second operation, and
substantially maintaining the first and second select lines to the turn-off voltage level during the fourth operation.
11 . An operating method of a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines, the operating method comprising:
selecting at least one of the plurality of memory blocks as a selected memory block; and
performing a read refresh operation on the selected memory block,
wherein the read refresh operation includes:
a first operation of driving a first voltage level to each of the plurality of word lines,
a second operation of discharging, after the first operation, each of the plurality of word lines to a second voltage level,
a third operation of driving, after the second operation, a third voltage level less than the first voltage level to each of the plurality of word lines, and
a fourth operation of discharging, after the third operation, each of the plurality of word lines to a fourth voltage level,
wherein the first voltage level is a level higher by a set level than a voltage level for turning on a memory cell with a highest threshold voltage level among the plurality of memory cells, and
wherein the third voltage level is a level for turning on some of the plurality of memory cells and turning off the others.
12 . The operating method of claim 11 , wherein each of the second voltage level and the fourth voltage level is a ground voltage level.
13 . The operating method of claim 11 ,
wherein each of the plurality of memory blocks further includes a first select line and a second select line, the plurality of word lines being arranged between the first select line and the second select line, and
wherein the read refresh operation further includes:
substantially maintaining the first and second select lines to a turn-on voltage level during the first operation or the third operation,
substantially maintaining the first and second select lines to one of the turn-on voltage level and a turn-off voltage level during the second operation, and
substantially maintaining the first and second select lines to the turn-off voltage level during the fourth operation.