HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE
Techniques for task processing using a highly parallel processing architecture with a shallow pipeline are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, microcode control words generated by the compiler. Relevant portions of the control word are stored within a cache associated with the array of compute elements. The control words are decompressed. The decompressing occurs cycle-by-cycle out of the cache over multiple cycles. A compiled task is executed on the array of compute elements, based on the decompressing. Simultaneous execution of two or more potential compiled task outcomes is provided.
1 . A processor-implemented method for task processing comprising:
accessing a two-dimensional (2D) array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide, variable length, microcode control words generated by the compiler;
decompressing the control words to enable control on a per element basis; and
executing a compiled task on the array of compute elements, wherein the executing is based on the control words that were decompressed.
2 . The method of claim 1 further comprising storing relevant portions of the control word within a cache associated with the array of compute elements.
3 . The method of claim 2 wherein the decompressing occurs cycle-by-cycle out of the cache.
4 . The method of claim 3 wherein decompressing of a single control word occurs over multiple cycles.
5 . The method of claim 4 wherein the multiple cycles accommodate control word straddle over a cache line fetch boundary.
6 . The method of claim 2 wherein the cache comprises a dual read, single write (2R1 W) cache.
7 . The method of claim 6 wherein the 2R1 W cache supports simultaneous fetch of potential branch paths for the compiled task.
8 . The method of claim 2 wherein the cache enables the control word to be distributed across a row of the array of compute elements.
9 . The method of claim 8 wherein the distribution across a row of the array of compute elements is accomplished in one cycle.
10 . The method of claim 1 further comprising providing simultaneous execution of two or more potential compiled task outcomes.
11 . The method of claim 10 wherein the two or more potential compiled task outcomes comprise a computation result or a routing control.
12 . The method of claim 10 wherein the two or more potential compiled outcomes are controlled by the same control word.
13 . The method of claim 12 wherein the same control word is executed on a given cycle across the array of compute elements.
14 . The method of claim 13 wherein the two or more potential compiled outcomes are executed on spatially separate compute elements within the array of compute elements.
15 . The method of claim 1 wherein the compiled task determines an unneeded compute element within a row of compute elements within the array of compute elements.
16 . The method of claim 15 wherein the unneeded compute element is controlled by a single bit in the control word.
17 . The method of claim 1 wherein the compiled task includes a spatial allocation of subtasks on one or more compute elements within the array of compute elements.
18 . The method of claim 17 wherein the spatial allocation provides for an idle compute element row and/or column in the array of compute elements.
19 . The method of claim 18 wherein the idle compute element row is controlled by a single bit in the control word.
20 . The method of claim 18 wherein the idle compute element column is controlled by a single bit in the control word.
21 . The method of claim 1 wherein the compiled task schedules computation in the array of compute elements.
22 . The method of claim 21 wherein the computation includes compute element placement, results routing, and computation wave-front propagation within the array of compute elements.
23 . The method of claim 1 wherein compute elements within the array of compute elements have identical functionality.
24 . (canceled)
25 . The method of claim 1 wherein the compiled task includes multiple programming loop instances circulating within the array of compute elements.
26 - 28 . (canceled)
29 . A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:
accessing a two-dimensional (2D) array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide, variable length, microcode control words generated by the compiler;
decompressing the control words to enable control on a per element basis; and
executing a compiled task on the array of compute elements, wherein the executing is based on the control words that were decompressed.
30 . A computer system for task processing comprising:
a memory which stores instructions;
one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
access a two-dimensional (2D) array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
provide control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide, variable length, microcode control words generated by the compiler;
decompress the control words to enable control on a per element basis; and
execute a compiled task on the array of compute elements, wherein the executing is based on the control words that were decompressed.