IP Library Granted Patent US 11,967,622
Granted Patent B2
US 11,967,622 · App. 17/466,205 · Granted Apr 23, 2024

Inter block for recessed contacts and methods forming same

Inventors: Te-Chih Hsiung (Taipei, TW); Jyun-De Wu (Hsinchu, TW); Yi-Chen Wang (Hsinchu, TW); Yi-Chun Chang (Hsinchu, TW); Yuan-Tien Tu (Puzih, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/41791H01L21/76804H01L21/76816H01L21/76831H01L21/823418H01L21/823431H01L21/823475H01L23/5226H01L23/5283H01L23/53266H01L27/0886H01L29/401H01L29/4236H01L29/66795H01L29/7851
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Quick Facts
Patent No.
US 11,967,622
App. No.
17/466,205
Granted
Apr 23, 2024
Kind
B2
Abstract

Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Claims (42)

1. A method comprising:

forming a metallic region in a first insulating layer;

forming a recess in the metallic region;

filling the recess with an inter block dielectric;

depositing a second insulating layer over the metallic region and the first insulating layer;

forming a first conductive structure extending through the second insulating layer and extending into the metallic region; and

forming a second conductive structure extending through the second insulating layer and extending into the metallic region, the first conductive structure being on a first side of the inter block dielectric, the second conductive structure being on a second side of the inter block dielectric, the second side being opposite the first side.

2. The method of claim 1 , wherein forming the first conductive structure comprises:

performing a first etching process to etch the second insulating layer to form a first opening in the second insulating layer, the first opening exposing a portion of the metallic region; and

performing a second etching process through the first opening to etch a first depression into an upper surface of the metallic region, the first depression having greater lateral extents than a bottom of the first opening.

3. The method of claim 2 , wherein performing the second etching process exposes a side wall of the inter block dielectric.

4. The method of claim 1 , wherein the first conductive structure or the second conductive structure contacts the inter block dielectric.

5. The method of claim 1 , wherein the first conductive structure comprises a different material composition than the metallic region, wherein forming the second conductive structure comprises:

forming a third opening in the second insulating layer; and

performing a third etching process through the third opening to etch a second depression into an upper surface of the metallic region, wherein the inter block dielectric prevents etchant from the third etching process from contacting an interface between the first conductive structure and the metallic region.

6. The method of claim 1 , wherein the inter block dielectric has tapered sidewalls.

7. The method of claim 1 , wherein the recess traverses an entire width of the metallic region.

8. The method of claim 1 , wherein an upper portion of the first conductive structure is offset a side-to-side center of a lower portion of the first conductive structure.

9. The method of claim 1 , wherein the metallic region comprises cobalt, and wherein the first conductive structure comprises tungsten.

10. A method comprising:

forming a first conductive feature in a first insulating layer, the first conductive feature having a recess;

forming an inter block dielectric in the recess;

depositing a second insulating layer over the first conductive feature and the first insulating layer; and

forming a first conductive structure and a second conductive structure through the second insulating layer to the first conductive feature, the first conductive structure contacts the first conductive feature on a first side of the inter block dielectric, the second conductive structure contacts the first conductive feature on a second side of the inter block dielectric.

11. The method of claim 10 , wherein forming the first conductive structure and the second conductive structure comprises:

forming the first conductive structure; and

after forming the first conductive structure, forming the second conductive structure.

12. The method of claim 10 , wherein the first conductive structure extends into the first conductive feature.

13. The method of claim 10 , wherein the first conductive structure contacts the inter block dielectric.

14. The method of claim 10 , wherein an upper surface of the inter block dielectric is level with an upper surface of the first conductive feature.

15. A method comprising:

forming a first insulating layer;

forming a first conductive feature in the first insulating layer, the first conductive feature having an upper surface level with an upper surface of the first insulating layer;

forming an inter block dielectric in the first conductive feature, the inter block dielectric having an upper surface level with the upper surface of the first conductive feature, the inter block dielectric having a bottom surface disposed between a bottom surface of the first conductive feature and the upper surface of the first conductive feature;

forming a second insulating layer over the first insulating layer;

forming a first contact in the second insulating layer, the first contact being electrically coupled to the first conductive feature; and

forming a second contact in the second insulating layer, the second contact being electrically coupled to the first conductive feature, wherein the inter block dielectric is laterally between the first contact and the second contact.

16. The method of claim 15 , wherein forming the first contact comprises recessing the first conductive feature to form a first recess, wherein the first contact extends into the first recess.

17. The method of claim 15 , wherein the inter block dielectric has tapered sidewalls.

18. The method of claim 15 , wherein the inter block dielectric has a non-flat bottom surface.

19. The method of claim 15 , wherein the first contact comprises a different material than the second contact.

20. The method of claim 15 , wherein the first contact contacts a sidewall of the inter block dielectric.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2021
From: HSIUNG, TE-CHIH; WU, JYUN-DE; WANG, YI-CHEN; CHANG, YI-CHUN; TU, YUAN-TIEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 057381/0657 →
Continuity (2)
Provisional Application 63184550 · May 5, 2021
Related Publication 20220359684A1 · Nov 10, 2022