Streaming engine with cache-like stream data storage and lifetime tracking
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.
1. A circuit device comprising:
a set of functional units;
a cache memory:
a memory access circuit coupled between the set of functional units and the cache memory, wherein the memory access circuit includes:
a memory interface coupled to the cache memory;
a buffer coupled to the memory interface that includes a set of lines, wherein:
each line of the set of lines is configured to store an address, data associated with the address, and a set of indicators; and
the set of indicators indicates whether the respective data is stored in the respective line and whether a request for the respective data is pending with the cache memory; and
a storage tracking unit configured to:
receive a set of requested addresses; and
for each requested address in the set of requested addresses:
determine, based on the sets of indicators in the buffer, whether data associated with the requested address is stored in the buffer,
when the data associated with the requested address is not stored in the buffer, provide a respective command to the memory interface requesting the data associated with the requested address;
when the data associated with the requested address is stored in the buffer, inhibit the respective command to the memory interface requesting the data associated with the requested address; and
when a first command for the data associated the requested address is pending with the cache memory, inhibit a second command to the memory interface requesting the data associated with the requested address.
2. The circuit device of claim 1 , wherein the set of indicators further indicates, for each line of the set of lines, whether the respective line is available for allocation.
3. The circuit device of claim 1 , wherein the set of indicators includes, for each line of the set of lines:
a valid indicator indicating whether the respective address is valid; and
a ready indicator indicating whether the respective data is stored in the buffer.
4. The circuit device of claim 1 , wherein:
the memory access circuit further includes a stream head register coupled between the buffer and the set of functional units; and
the stream head register is configured to provide a set of data associated with the set of requested addresses from the buffer to the set of functional units as a data stream.
5. The circuit device of claim 1 , wherein the cache memory includes a level-two (L2) cache memory and the memory interface is coupled to the L2 cache memory.
6. The circuit device of claim 5 , wherein the cache memory includes a level-one (L1) cache memory and the memory interface is coupled to the L2 cache memory via a datapath that does not include the L1 cache memory.
7. A circuit device comprising:
a set of functional units;
a cache memory;
a memory access circuit coupled between the set of functional units and the cache memory, wherein the memory access circuit includes:
a memory interface coupled to the cache memory;
a command queue;
a buffer coupled to the memory interface that includes a set of lines, wherein:
each line of the set of lines is configured to store an address, data associated with the address, and a set of indicators; and
the set of indicators indicate whether the respective data is stored in the respective line; and
a storage tracking unit configured to:
receive a set of requested addresses;
for each requested address in the set of requested addresses:
determine, based on the sets of indicators in the buffer, whether data associated with the requested address is stored in the buffer,
when the data associated with the requested address is not stored in the buffer, provide a respective command to the memory interface requesting the data associated with the requested address; and
when the data associated with the requested address is stored in the buffer, inhibit the respective command to the memory interface requesting the data associated with the requested address; and
when a first set of data associated with a first requested address is stored in the buffer, inhibit a first command for the first set of data by cancelling the first command in the command queue.
8. The circuit device of claim 7 , wherein the set of indicators further indicates, for each line of the set of lines, whether a request for the respective data associated with the respective line is pending with the cache memory.
9. The circuit device of claim 7 , wherein the cache memory includes a level-two (L2) cache memory and the memory interface is coupled to the L2 cache memory.
10. A circuit device comprising:
a set of functional units;
a cache memory;
a memory access circuit coupled between the set of functional units and the cache memory, wherein the memory access circuit includes:
a memory interface coupled to the cache memory;
a buffer coupled to the memory interface that includes a set of lines, wherein:
each line of the set of lines is configured to store an address, data associated with the address, and a set of indicators;
the set of indicators indicate whether the respective data is stored in the respective line; and
the set of indicators includes, for each line of the set of lines:
a valid indicator indicating whether the respective address is valid;
a ready indicator indicating whether the respective data is stored in the buffer; and
an active indicator indicating whether a reference to the respective data is in flight in the memory access circuit;
a storage tracking unit configured to:
receive a set of requested addresses; and
for each requested address in the set of requested addresses:
determine, based on the sets of indicators in the buffer, whether data associated with the requested address is stored in the buffer,
when the data associated with the requested address is not stored in the buffer, provide a respective command to the memory interface requesting the data associated with the requested address; and
when the data associated with the requested address is stored in the buffer, inhibit the respective command to the memory interface requesting the data associated with the requested address.
11. The circuit device of claim 10 , wherein the cache memory includes a level-two (L2) cache memory and the memory interface is coupled to the L2 cache memory.
12. A circuit device comprising:
a processor core configured to provide an instruction that requests a set of data;
a cache memory;
a memory access circuit coupled between the processor core and the cache memory. wherein the memory access circuit includes:
an address generator coupled to the processor core and configured to produce, based on the instruction, a set of addresses associated with the set of data;
a buffer that includes a set of lines each configured to store a respective unit of data, wherein:
the buffer is configured to store a set of indicators associated with the set of lines; and
the set of indicators indicates, for each line of the set of lines, whether a request for data to be stored in the respective line is pending with the cache memory;
a memory interface coupled to the cache memory; and
a storage tracking unit coupled to the buffer, to the address generator, and to the memory interface and configured to:
for each address of the set of addresses:
determine, based on the set of indicators in the buffer, whether a unit of data associated with the respective address is stored in the buffer;
when the unit of data associated with the respective address is not stored in the buffer, provide a respective command to the memory interface requesting the unit of data associated with the respective address;
when the unit of data associated with the respective address is stored in the buffer, inhibit the respective command to the memory interface requesting the unit of data associated with the respective address; and
when a first command for the unit of data associated with the respective address is pending with the cache memory, inhibit a second command to the memory interface requesting the unit of data associated with the respective address.
13. The circuit device of claim 12 , wherein the set of addresses associated with the instruction includes a plurality of addresses.
14. The circuit device of claim 12 , wherein the set of indicators indicates, for each line of the set of lines, whether the respective line is available for allocation.
15. The circuit device of claim 12 , wherein the set of indicators includes, for each line of the set of lines:
a valid indicator indicating whether an address associated with the line is valid; and
a ready indicator indicating whether data associated with the line is stored in the buffer.
16. The circuit device of claim 12 , wherein:
the memory access circuit further includes a stream head register coupled to the processor core; and
the stream head register is configured to provide the set of data associated with the instruction from the buffer to processor core as a data stream.
17. The circuit device of claim 12 , wherein the cache memory includes a level-two (L2) cache memory and the memory interface is coupled to the L2 cache memory.
18. The circuit device of claim 17 , wherein the cache memory includes a level-one (L1) cache memory and the memory interface is coupled to the L2 cache memory via a datapath that does not include the L1 cache memory.
19. A circuit device comprising:
a processor core configured to provide an instruction that requests a set of data;
a cache memory;
a memory access circuit coupled between the processor core and the cache memory, wherein the memory access circuit includes:
an address generator coupled to the processor core and configured to produce, based on the instruction, a set of addresses associated with the set of data;
a buffer that includes a set of lines each configured to store a respective unit of data, wherein:
the buffer is configured to store a set of indicators associated with the set of lines; and
the set of indicators includes, for each line of the set of lines:
a valid indicator indicating whether an address associated with the line is valid;
a ready indicator indicating whether data associated with the line is stored in the buffer; and
an active indicator indicating whether a reference to the data associated with the line is in flight in the memory access circuit
a memory interface coupled to the cache memory; and
a storage tracking unit coupled to the buffer, to the address generator, and to the memory interface and configured to:
for each address of the set of addresses:
determine, based on the set of indicators in the buffer, whether a unit of data associated with the respective address is stored in the buffer;
when the unit of data associated with the respective address is not stored in the buffer, provide a respective command to the memory interface requesting the unit of data associated with the respective address; and
when the unit of data associated with the respective address is stored in the buffer, inhibit the respective command to the memory interface requesting the unit of data associated with the respective address.
20. The circuit device of claim 19 , wherein the cache memory includes a level-two (L2) cache memory and the memory interface is coupled to the L2 cache memory.