Semiconductor integrated circuit and arithmetic system
According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.
1. A semiconductor integrated circuit comprising:
a global circuit; and
a plurality of DA converters connected to the global circuit,
each of the plurality of DA converters including
a current source,
a capacitive element having a first end and a second end, the second end being connected to a node of a reference potential of the DA converter,
an amplifier circuit having an input node,
a first switch element having a first end connected to the current source and a second end connected to the first end of the capacitive element,
a second switch element having a first end connected to the first end of the capacitive element and a second end connected to the node of the reference potential,
a third switch element having a first end connected to the first end of the capacitive element and a second end connected to the input node of the amplifier circuit, and
a control circuit configured to maintain the second switch element in an on state while maintaining the first switch element and the third switch element both in an off state in a first period, and to maintain the first switch element in an on state while maintaining the second switch element and the third switch element both in an off state in a second period after the first period, wherein
end timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal received from the global circuit.
2. The semiconductor integrated circuit according to claim 1 , wherein
the control circuit is configure to maintain the first switch element, the second switch element, and the third switch element in an off state in a third period between the first period and the second period.
3. The semiconductor integrated circuit according to claim 2 , wherein
the control circuit is further configure to maintain the third switch element in an on state while maintaining the first switch element and the second switch element in an off state in a fourth period after the second period.
4. The semiconductor integrated circuit according to claim 2 , wherein
the global circuit includes a global counter, and is configure to output a start signal at start of counting of the global counter and to output a stop signal at finish of counting of the global counter, and
the control circuit includes a local counter connected to the global circuit, and the local counter is configure to count up from a value of an input digital signal to a maximum value in the third period that starts in response to the start signal received from the global circuit and to count up from a minimum value to the value of the input digital signal in the second period that starts in response to a count value of the local counter reaching the maximum value and ends in response to the stop signal received from the global circuit.
5. The semiconductor integrated circuit according to claim 2 , wherein
start timings of the third period in the plurality of DA converters are synchronized with each other, and start timings of the second period in the plurality of DA converters are not synchronized with each other.
6. The semiconductor integrated circuit according to claim 2 , wherein
a total length of the third period and the second period is substantially equal among the plurality of DA converters.
7. The semiconductor integrated circuit according to claim 1 , wherein
start timings of the second period in the plurality of DA converters are not synchronized with each other.
8. A semiconductor integrated circuit comprising:
a global circuit; and
a plurality of DA converters connected to the global circuit,
each of the plurality of DA converters including
a variable current source having a control end,
a first capacitive element having a first end connected to a first node and a second end connected to a node of a reference potential of the DA converter,
a second capacitive element having a first end connected to the control end of the variable current source and a second end connected to a node of a power supply potential of the DA converter,
a differential amplifier circuit having a first input node to which a reference signal is supplied from the global circuit, a second input node connected to the first node, and an output node,
a first switch element having a first end connected to the first node and a second end connected to the node of the reference potential,
a second switch element having a first end connected to the control end of the variable current source and a second end connected to the node of the power supply potential,
a third switch element having a first end connected to the control end of the variable current source and a second end connected to the output node of the differential amplifier circuit, and
a fourth switch element having a first end connected to the variable current source and a second end connected to the first node.
9. The semiconductor integrated circuit according to claim 8 , further comprising
an inverter connected between the differential amplifier circuit and the third switch element.
10. The semiconductor integrated circuit according to claim 9 , wherein
the inverter includes a first transistor and a second transistor, the first transistor and the second transistor being inverter-connected between the differential amplifier circuit and the third switch element.
11. The semiconductor integrated circuit according to claim 8 , further comprising:
an amplifier circuit having an input node; and
a fifth switch element having a first end connected to the first node and a second end connected to the input node of the amplifier circuit.
12. The semiconductor integrated circuit according to claim 8 , wherein
each of the plurality of DA converters further includes a control circuit configured, in a first period, to maintain the first switch element and the second switch element both in an on state while maintaining the third switch element and the fourth switch element both in an off state, and in a second period after the first period, to maintain the third switch element and the fourth switch element both in an on state while maintaining the first switch element and the second switch element both in an off state.
13. The semiconductor integrated circuit according to claim 8 , wherein
the variable current source includes series connection of a first transistor and a second transistor between the node of the power supply potential and the fourth switch element.
14. The semiconductor integrated circuit according to claim 13 , wherein
the first transistor has a gate connected to the first end of the second capacitive element, a source connected to the node of the power supply, and a drain connected to the second transistor, and
the second transistor has a gate to which a bias voltage is supplied, a source connected to the first transistor, and a drain to which the fourth switch is connected.
15. An arithmetic system comprising:
the semiconductor integrated circuit according to claim 1 , the semiconductor integrated circuit being configured to generate a plurality of first signals;
a plurality of multiplier elements configured to multiply the plurality of first signals by weights independent of each other to generate a plurality of calculation results, the multiplier elements being arranged to constitute a plurality of rows and a plurality of columns; and
a plurality of adder elements configured to calculate, for each of the plurality of columns, a sum of calculation results of each column among the plurality of calculation results to generate a plurality of second signals.
16. The arithmetic system according to claim 15 , wherein
the control circuit is configured to maintain the first switch element, the second switch element, and the third switch element in an off state in a third period between the first period and the second period.
17. The arithmetic system according to claim 15 , wherein
start timings of the second period in the plurality of DA converters are not synchronized with each other.
18. An arithmetic system comprising:
the semiconductor integrated circuit according to claim 10 , the semiconductor integrated circuit being configured to generate a plurality of first signals;
a plurality of multiplier elements configured to multiply the plurality of first signals by weights independent of each other to generate a plurality of calculation results, the multiplier elements being arranged to constitute a plurality of rows and a plurality of columns; and
a plurality of adder elements configured to calculate, for each of the plurality of columns, a sum of calculation results of each column among the plurality of calculation results to generate a plurality of second signals.
19. The arithmetic system according to claim 18 , wherein
the semiconductor integrated circuit further includes an inverter connected between the differential amplifier circuit and the third switch element.
20. The arithmetic system according to claim 18 , wherein
each of the plurality of DA converters further includes a control circuit configured, in a first period, to maintain the first switch element and the second switch element both in an on state while maintaining the third switch element and the fourth switch element both in an off state, and in a second period after the first period, to maintain the third switch element and the fourth switch element both in an on state while maintaining the first switch element and the second switch element both in an off state.