Semiconductor device and semiconductor system including electro static discharge (ESD) protective device
View Patent ↗According to one embodiment, a first P-type transistor with a gate is coupled to a first node, and a drain is coupled to a second node. A first N-type transistor with a gate is coupled to the first node, and a drain is coupled to the second node. A second P-type transistor with a gate is coupled to the second node, and a drain is coupled to a third node. A second N-type transistor with a gate is coupled to the second node, and a drain is coupled to the third node. The first P-type transistor is smaller than the first N-type transistor. The second N-type transistor is smaller than the second P-type transistor. The second N-type transistor is smaller than the first N-type transistor.
1. A semiconductor device formed on a silicon on insulator (SOI) substrate including a substrate, an insulating layer provided on the substrate, and a semiconductor layer provided on the insulating layer, the semiconductor device comprising:
a first power line;
a second power line;
a plurality of first diodes coupled in series between the first power line and a first node, with anodes on a first power line side;
a first resistor coupled between the first node and the second power line;
a first P-type transistor with a gate coupled to the first node, a source coupled to the first power line, a body coupled to the first power line, and a drain coupled to a second node;
a first N-type transistor with a gate coupled to the first node, a source coupled to the second power line, a body coupled to the second power line, and a drain coupled to the second node;
a second P-type transistor with a gate coupled to the second node, a source coupled to the first power line, a body coupled to the first power line, and a drain coupled to a third node;
a second N-type transistor with a gate coupled to the second node, a source coupled to the second power line, a body coupled to the second power line, and a drain coupled to the third node; and
a third N-type transistor with a gate coupled to the third node, a source coupled to the second power line, a body coupled to the second power line, and a drain coupled to the first power line, wherein
a value obtained by dividing a gate width of the first P-type transistor by a gate length thereof is smaller than a value obtained by dividing a gate width of the first N-type transistor by a gate length thereof,
a value obtained by dividing a gate width of the second N-type transistor by a gate length thereof is smaller than a value obtained by dividing a gate width of the second P-type transistor by a gate length thereof,
the value obtained by dividing the gate width of the second N-type transistor by the gate length thereof is smaller than the value obtained by dividing the gate width of the first N-type transistor by the gate length thereof,
the value obtained by dividing the gate width of the first N-type transistor by the gate length thereof is smaller than a value obtained by dividing a gate width of the third N-type transistor by a gate length thereof,
the semiconductor layer includes:
a first N-type diffusion region and second N-type diffusion region extending in a first direction and provided adjacent to each other in a second direction which intersects the first direction;
a third N-type diffusion region extending in the first direction and provided between the first N-type diffusion region and the second N-type diffusion region in the second direction;
a first P-type diffusion region including a first portion provided between the first N-type diffusion region and the third N-type diffusion region, a second portion provided between the second N-type diffusion region and the third N-type diffusion region, a third portion configured to divide the third N-type diffusion region in the first direction and couple the first portion to the second portion; and
a second P-type diffusion region surrounded by the third N-type diffusion region and the third portion of the first P-type diffusion region and in contact with the third portion of the first P-type diffusion region in the first direction
the semiconductor device further comprises:
a first contact provided on the third N-type diffusion region;
a second contact provided on the second P-type diffusion region; and
an interconnect coupled to the first contact and the second contact,
the first N-type diffusion region and the second N-type diffusion region function as the drain of the third N-type transistor,
the third N-type diffusion region functions as the source of the third N-type transistor, and
the P-type diffusion region functions as the body of the third N-type transistor.
2. The semiconductor device according to claim 1 , further comprising:
a second diode with an anode coupled to the second power line and a cathode coupled to the first power line, wherein
an area of a p-n junction of each of the first diodes is smaller than an area of a p-n junction of the second diode.
3. The semiconductor device according to claim 1 , wherein each of the first and second P-type transistors and the first to third N-type transistors is a fully depleted transistor.
4. The semiconductor device according to claim 1 , further comprising:
a signal line;
a third diode with an anode coupled to the signal line and a cathode coupled to the first power line; and
a fourth diode with an anode coupled to the second power line and a cathode coupled to the signal line, wherein
an area of a p-n junction of each of the third and fourth diodes is larger than an area of a p-n junction of each of the first diodes.
5. The semiconductor device according to claim 1 , wherein
the semiconductor layer includes a first diffusion region, a third P-type diffusion region in contact with the first diffusion region, and a fourth N-type diffusion region in contact with the first diffusion region,
the semiconductor device further comprises:
an oxide film provided on the first diffusion region; and
a conductor provided on the oxide film,
the third P-type diffusion region and the fourth N-type diffusion region interpose the first diffusion region therebetween,
the first diffusion region is a P-type diffusion region or an N-type diffusion region,
the conductor is in an electrically-floating state, and
a contact surface between the first diffusion region and the third P-type diffusion region or a contact surface between the first diffusion region and the fourth N-type diffusion region functions as part of the first diodes.
6. The semiconductor device according to claim 5 , wherein
when the first diffusion region is a P-type diffusion region, a concentration of P-type impurities included in the first diffusion region is lower than a concentration of P-type impurities included in the third P-type diffusion region, and
when the first diffusion region is an N-type diffusion region, a concentration of N-type impurities included in the first diffusion region is lower than a concentration of N-type impurities included in the fourth N-type diffusion region.
7. A semiconductor system comprising:
the semiconductor device according to claim 1 ;
a first terminal coupled to the first power line;
a second terminal coupled to the second power line; and
a second semiconductor device coupled to the first power line and the second power line and configured to amplify a radio-frequency signal, wherein
the second semiconductor device is operated by a first voltage being applied between the first terminal and the second terminal, and
a sum of forward voltages of the first diodes is larger than the first voltage.
8. The semiconductor system according to claim 7 , wherein
the semiconductor device further comprises a second diode with an anode coupled to the second power line and a cathode coupled to the first power line, and
an area of a p-n junction of each of the first diodes is smaller than an area of a p-n junction of the second diode.
9. The semiconductor system according to claim 7 , wherein each of the first and second P-type transistors and the first to third N-type transistors is a fully depleted transistor.
10. The semiconductor system according to claim 7 , wherein
the semiconductor device further comprises:
a signal line;
a third diode with an anode coupled to the signal line and a cathode coupled to the first power line; and
a fourth diode with an anode coupled to the second power line and a cathode coupled to the signal line, and
an area of a p-n junction of each of the third and fourth diodes is larger than an area of a p-n junction of each of the first diodes.
11. The semiconductor system according to claim 7 , wherein
the semiconductor layer of the semiconductor device includes a first diffusion region, a third P-type diffusion region in contact with the first diffusion region, and a fourth N-type diffusion region in contact with the first diffusion region,
the semiconductor device further comprises:
an oxide film provided on the first diffusion region; and
a conductor provided on the oxide film,
the third P-type diffusion region and the fourth N-type diffusion region interpose the first diffusion region therebetween,
the first diffusion region is a P-type diffusion region or an N-type diffusion region,
the conductor is in an electrically-floating state, and
a contact surface between the first diffusion region and the third P-type diffusion region or a contact surface between the first diffusion region and the fourth N-type diffusion region functions as part of the first diodes.
12. The semiconductor system according to claim 11 , wherein
when the first diffusion region is a P-type diffusion region, a concentration of P-type impurities included in the first diffusion region is lower than a concentration of P-type impurities included in the third P-type diffusion region, and
when the first diffusion region is an N-type diffusion region, a concentration of N-type impurities included in the first diffusion region is lower than a concentration of N-type impurities included in the fourth N-type diffusion region.