Dynamic inhibit voltage to reduce write power for random-access memory
In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
1. A memory device comprising:
a first voltage regulator to receive a word line voltage provided to a memory array;
a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and
a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
2. The memory device of claim 1 , wherein the resistor network is coupled to ground.
3. The memory device of claim 1 , wherein the resistor network is coupled to a current mirror to receive a bias current.
4. The memory device of claim 3 , wherein the current mirror is coupled to a plurality of memory cells and the bias current is at least based on a leakage current of the plurality of memory cells.
5. The memory device of claim 4 , wherein a third voltage regulator is coupled between the current mirror and the plurality of memory cells and the third voltage regulator biases at least a bit line and select line of the plurality of memory cells.
6. The memory device of claim 4 , wherein the plurality of memory cells is an unselected portion of the memory array.
7. The memory device of claim 4 , wherein the plurality of memory cells is separate from the memory array.
8. The memory device of claim 1 , wherein the inhibit voltage is less than the word line voltage by a fixed delta.
9. The memory device of claim 1 , wherein the inhibit voltage is proportional to the word line voltage.