Device and method for updating register transfer level power model
Provided are a device and method for updating a register transfer level (RTL) power model for power consumption analysis of a semiconductor circuit by at least one processor. The method includes receiving a test scenario including a plurality of time slots, inputting the test scenario to an initial power model and identifying a first set of time slots related to a power state which is not defined by the initial power model among the plurality of time slots, determining a power value for a specific power state related to a second set of time slots which is a subset of the first set of time slots, and updating the initial power model on the basis of the specific power state and the determined power value. Each of the plurality of time slots is related to one power state.
1. A method of updating a register transfer level (RTL) power model for power consumption analysis of a semiconductor circuit by at least one processor, the method comprising:
receiving a test scenario including a plurality of time slots, each of which is related to one power state;
inputting the test scenario to an initial power model and identifying a first set of time slots related to a power state which is not defined by the initial power model among the plurality of time slots;
determining a power value for a specific power state related to a second set of time slots which is a subset of the first set of time slots through a gate-level simulation of the semiconductor circuit; and
updating the initial power model on the basis of the specific power state and the determined power value,
wherein the inputting of the test scenario to the initial power model and the identifying of the first set of time slots related to the power state which is not defined by the initial power model among the plurality of time slots comprises:
identifying a specific time slot section including a predetermined ratio of time slots or more related to the power state not defined by the initial power model among the plurality of time slots; and
identifying the time slots related to the power state not defined by the initial power model among time slots in the specific time slot section as the first set of time slots.
2. The method of claim 1 , further comprising:
receiving a training vector including a plurality of power states and power values for the plurality of power states; and
generating the initial power model on the basis of the training vector.
3. The method of claim 1 , wherein the determining of the power value for the specific power state related to the second set of time slots which is the subset of the first set of time slots comprises:
determining a power value in each of the second set of time slots through a gate-level simulation of the semiconductor circuit; and
determining an average of the power values in the second set of time slots as the power value for the specific power state.
4. The method of claim 1 , wherein, when the semiconductor circuit has n (n is a natural number) major input signals, 2 n power states are related to the semiconductor circuit, and
the 2 n power states are related to power values which differ from each other by a predetermined threshold value or more.
5. The method of claim 1 , wherein the determining of the power value for the specific power state related to the second set of time slots which is the subset of the first set of time slots comprises:
determining a power value in each of the second set of time slots by performing the gate-level simulation of the semiconductor circuit for the specific time slot section; and
determining an average of the power values in the second set of time slots as the power value for the specific power state.
6. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1 .
7. A device comprising:
a memory; and
at least one processor connected to the memory and configured to execute at least one computer-readable program included in the memory,
wherein the at least one program includes instructions for:
receiving a test scenario including a plurality of time slots, each of which is related to one power state;
inputting the test scenario to an initial power model and identifying a first set of time slots related to a power state which is not defined by the initial power model among the plurality of time slots;
determining a power value for a specific power state related to a second set of time slots which is a subset of the first set of time slots through a gate-level simulation of a semiconductor circuit; and
updating the initial power model on the basis of the specific power state and the determined power value,
wherein the inputting of the test scenario to the initial power model and the identifying of the first set of time slots related to the power state which is not defined by the initial power model among the plurality of time slots comprises:
identifying a specific time slot section including a predetermined ratio of time slots or more related to the power state not defined by the initial power model among the plurality of time slots; and
identifying the time slots related to the power state not defined by the initial power model among time slots in the specific time slot section as the first set of time slots.