Semiconductor memory devices

1. A semiconductor memory device, comprising:

a substrate;

a semiconductor pattern extending in a first horizontal direction on the substrate;

bit lines extending in a second horizontal direction on the substrate, the second horizontal direction being perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern;

word lines extending in a vertical direction on the substrate, the word lines being at a side of the semiconductor pattern;

a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and

a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode, the capacitor contact layer including a pair of convex surfaces in contact with the semiconductor pattern.

2. The semiconductor memory device as claimed in claim 1 , wherein:

the second end of the semiconductor pattern includes a pair of recessed portions, and

the pair of recessed portions are mirror symmetrical to each other in the second horizontal direction with respect to a center line bisecting the semiconductor pattern in the first horizontal direction.

3. The semiconductor memory device as claimed in claim 2 , wherein:

the pair of convex surfaces are in contact with the pair of recessed portions and are mirror symmetrical to each other in the second horizontal direction with respect to the center line, and

the capacitor contact layer includes a metal silicide.

4. The semiconductor memory device as claimed in claim 1 , wherein:

the lower electrode includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and

the pair of first sidewalls are concave inward toward a center of the lower electrode.

5. The semiconductor memory device as claimed in claim 1 , wherein:

the lower electrode includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and

the pair of first sidewalls each include a plurality of curved portions.

6. The semiconductor memory device as claimed in claim 1 , further comprising two support layers extending in the first horizontal direction and spaced apart from each other in the vertical direction,

wherein the lower electrode is between the two support layers.

7. The semiconductor memory device as claimed in claim 6 , wherein a top surface of the lower electrode is in contact with one of the support layers and is flat.

8. The semiconductor memory device as claimed in claim 6 , wherein:

the lower electrode includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and

the capacitor dielectric layer extends along the pair of first sidewalls of the lower electrode and sidewalls of the two support layers.

9. The semiconductor memory device as claimed in claim 1 , wherein:

the lower electrode has a first length in the first horizontal direction and a first width in the second horizontal direction, and

a ratio of the first length to the first width is about 5 to 400.

10. A semiconductor memory device, comprising:

a substrate;

a plurality of semiconductor patterns extending in a first horizontal direction on the substrate, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction;

a plurality of bit lines extending in a second horizontal direction on the substrate, the second horizontal direction being perpendicular to the first horizontal direction, the plurality of bit line being spaced apart from each other in the vertical direction and on a first end of each of the plurality of semiconductor patterns;

a plurality of word lines extending in the vertical direction on the substrate, the plurality of word lines being on sides of the plurality of semiconductor patterns;

a capacitor structure on a second end of each of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction;

a plurality of support layers between two adjacent lower electrodes among the plurality of lower electrodes; and

a plurality of capacitor contact layers between the second end of each of the plurality of semiconductor patterns and the plurality of lower electrodes,

wherein the second end of each of the plurality of semiconductor patterns includes a pair of recessed portions.

11. The semiconductor memory device as claimed in claim 10 , wherein:

each of the plurality of capacitor contact layers includes a pair of convex surfaces in contact with the pair of recessed portions of a corresponding one of the plurality of semiconductor patterns, and

the pair of recessed portions are mirror symmetrical to each other in the second horizontal direction with respect to a center line bisecting the corresponding one of the plurality of semiconductor patterns in the first horizontal direction.

12. The semiconductor memory device as claimed in claim 10 , wherein:

each of the plurality of lower electrodes includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and

the pair of first sidewalls are concave inward toward a center of each lower electrode.

13. The semiconductor memory device as claimed in claim 12 , wherein a top surface of each of the plurality of lower electrodes is in contact with one of the plurality of support layers and is flat.

14. The semiconductor memory device as claimed in claim 12 , wherein the capacitor structure further includes:

a capacitor dielectric layer on the pair of first sidewalls of each of the plurality of lower electrodes and sidewalls of the plurality of support layers; and

an upper electrode covering the plurality of lower electrodes and the capacitor dielectric layer.

15. The semiconductor memory device as claimed in claim 10 , wherein:

each of the plurality of lower electrodes includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and

the pair of first sidewalls each include a plurality of curved portions.

16. The semiconductor memory device as claimed in claim 10 , wherein:

each of the plurality of lower electrodes has a first length in the first horizontal direction and a first width in the second horizontal direction, and

a ratio of the first length to the first width is about 5 to 400.

17. A semiconductor memory device, comprising:

a substrate;

a plurality of semiconductor patterns extending in a first horizontal direction on the substrate, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction;

a plurality of bit lines extending in a second horizontal direction on the substrate, the second horizontal direction being perpendicular to the first horizontal direction, the plurality of bit lines being spaced apart from each other in the vertical direction, and being on a first end of each of the plurality of semiconductor patterns;

a pair of gate electrodes on the substrate and spaced apart from each other in the second horizontal direction, the pair of gate electrodes extending in the vertical direction and being on opposite sides of the plurality of semiconductor patterns;

a capacitor structure on a second end of each of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction;

a plurality of support layers alternately provided with the plurality of lower electrodes in the vertical direction; and

a plurality of capacitor contact layers between the second end of each of the plurality of semiconductor patterns and the plurality of lower electrodes, the plurality of capacitor contact layers including a metal silicide,

wherein the plurality of capacitor contact layers each include a pair of convex surfaces in contact with the plurality of semiconductor patterns.

18. The semiconductor memory device as claimed in claim 17 , wherein:

the second end of each of the plurality of semiconductor patterns includes a pair of recessed portions, and

the pair of recessed portions are mirror symmetrical to each other in the second horizontal direction with respect to a center line bisecting each semiconductor pattern in the first horizontal direction.

19. The semiconductor memory device as claimed in claim 17 , wherein:

each of the plurality of lower electrodes includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and

the pair of first sidewalls are concave inward toward a center of each lower electrode.

20. The semiconductor memory device as claimed in claim 17 , wherein:

each of the plurality of lower electrodes includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and

the pair of first sidewalls each include a plurality of curved portions.