Testing bit write operation to a memory array in integrated circuits

1. A method for testing a circuit, the method comprising:

performing, by a test engine, a test of bit write to a memory, the test comprising:

defining a set of bit write address bit groups and their respective decodes based on a set of input bits from an address to be tested of a memory location, wherein each respective decode comprises a multi-input, multi-output combination that converts a binary code of M input lines into one of N outputs, and wherein the set of input bits are taken from predetermined bit locations in the address;

generating an encoded binary number in a predetermined range of 1 to M based on the set of input bits from the address;

generating, from the encoded binary number, a decoded binary number in a predetermined range of 1 to N;

generating, from a bit pattern of the decoded binary number, a bit mask for the bit groups;

generating, from a bit pattern of the encoded binary number, expect data;

performing a bit write operation comprising a partial write to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern testing algorithm configured to test bit write capability;

reading a content of the address; and

comparing bits selected using the bit mask to the expect data.

2. The method of claim 1 , wherein the test engine is a built-in self-test engine of the circuit.

3. The method of claim 1 , further comprising:

repeating the test for a number of times equal to the encoded binary number.

4. The method of claim 1 , wherein the predetermined bit pattern is selected based on a predetermined selected algorithm.

5. The method of claim 4 , wherein the test is repeated with a plurality of predetermined bit patterns.

6. The method of claim 1 , wherein the set of bits from the address is a predetermined selection.

7. A system comprising:

a memory element that is to be tested;

a circuit that generates a dynamic bit mask;

a test engine coupled with the memory element and the circuit, the test engine configured to test a bit write operation to the memory element by performing a method comprising:

defining a set of bit write address bit groups and their respective decodes based on a set of input bits from an address to be tested of a memory location in the memory element, wherein each respective decode comprises a multi-input, multi-output combination that converts a binary code of M input lines into one of N outputs, and wherein the set of input bits are taken from predetermined bit locations in the address;

generating an encoded binary number in a predetermined range of 1 to M based on the set of input bits from the address;

generating, from the encoded binary number, a decoded binary number in a predetermined range of 1 to N;

generating, using the circuit, from a bit pattern of the decoded binary number, the dynamic bit mask for the bit groups;

generating, from a bit pattern of the encoded binary number, expect data;

performing a bit write operation comprising a partial write to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern testing algorithm configured to test bit write capability;

reading a content of the address; and

comparing bits selected using the dynamic bit mask to the expect data.

8. The system of claim 7 , wherein the test engine is a built-in self-test engine of the system.

9. The system of claim 7 , wherein the method further comprises:

repeating the test for a number of times equal to the encoded binary number.

10. The system of claim 7 , wherein the predetermined bit pattern is selected based on a predetermined selected algorithm.

11. The system of claim 10 , wherein the test is iterated with a plurality of predetermined bit patterns.

12. The system of claim 7 , wherein the set of bits from the address is a predetermined selection.

13. An apparatus for implementing diagnostics of a circuit, the apparatus comprising:

a test engine configured to test a memory element of the circuit by testing a bit write operation to the memory element by performing a method comprising;

defining a set of bit write address bit groups and their respective decodes based on a set of input bits from an address to be tested of a memory location in the memory element, wherein each respective decode comprises a multi-input, multi-output combination that converts a binary code of M input lines into one of N outputs, and wherein the set of input bits are taken from predetermined bit locations in the address;

generating an encoded binary number in a predetermined range of 1 to M based on the set of input bits from the address;

generating, from the encoded binary number, a decoded binary number in a predetermined range of 1 to N;

generating, using the circuit, from a bit pattern of the decoded binary number, the dynamic bit mask for the bit group;

generating, from a bit pattern of the encoded binary number, expect data;

performing a bit write operation comprising a partial write to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern testing algorithm configured to test bit write capability;

reading a content of the address; and

comparing bits selected using the dynamic bit mask to the expect data.

14. The apparatus of claim 13 , wherein the testing further comprises:

repeating the test for a number of times equal to the encoded binary number.

15. The apparatus of claim 13 , wherein the predetermined bit pattern is selected based on a predetermined selected algorithm.

16. The apparatus of claim 15 , wherein the test is iterated with a plurality of predetermined bit patterns.

17. The apparatus of claim 13 , wherein the set of bits from the address is a predetermined selection.