Baseline wander cancelation
A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.
1. An apparatus, comprising:
a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
an analog-to-digital converter circuit configured to sample, using a recovered clock signal, the equalized signal to generate a plurality of samples;
a recovery circuit configured to generate, using the plurality of samples, the recovered clock signal and a plurality of recovered data symbols;
a baseline wander control circuit configured to:
generate a disparity signal using the recovered data symbols, wherein the disparity signal is indicative of a difference in respective numbers of logic values included in the plurality of recovered data symbols; and
generate a gain signal and a control signal using the disparity signal; and
a digital-to-analog converter circuit configured to adjust respective input voltage levels of the plurality of signals using the gain signal and the control signal.
2. The apparatus of claim 1 , wherein to generate the disparity signal, the baseline wander control circuit is further configured to accumulate respective numbers of logic values included in the plurality of recovered data symbols.
3. The apparatus of claim 1 , wherein to generate the disparity signal, the baseline wander control circuit is further configured to perform an infinite impulse response filtering operation on at least a portion of the plurality of recovered data symbols.
4. The apparatus of claim 1 , wherein to adjust the respective input voltage levels of the plurality of signals, the digital-to-analog converter circuit is further configured to:
select a magnitude of a differential voltage level using the gain signal; and
couple, based on the control signal, the differential voltage level to at least one input of the front-end circuit.
5. The apparatus of claim 1 , wherein to generate the control signal, the baseline wander control circuit is further configured to:
perform a comparison of a running disparity and a plurality of threshold values, wherein the running disparity is based on the plurality of recovered data symbols; and
generate the control signal based on results of the comparison.
6. The apparatus of claim 1 , wherein to generate the gain signal, the baseline wander control circuit is further configured to:
perform a comparison of the disparity signal and a plurality of threshold values; and
multiply, based on results of the comparison, information indicative of errors detected during the generation of the plurality of recovered data symbols with the disparity signal or a filtered disparity signal.
7. A method, comprising:
receiving a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
generating an equalized signal using the plurality of signals;
sampling, using a recovered clock signal, the equalized signal to generate a plurality of samples;
generating the recovered clock signal and a plurality of recovered data symbols using the plurality of samples;
generating a disparity signal using the recovered data symbols, wherein the disparity signal is indicative of a difference in respective numbers of logic values included in the plurality of recovered data symbols; and
generating a gain signal and a control signal using the disparity signal; and
adjusting respective input voltage levels of the plurality of signals using the gain signal and the control signal.
8. The method of claim 7 , wherein generating the disparity signal includes accumulating the respective numbers of logic values included in the plurality of recovered data symbols in a rolling fashion.
9. The method of claim 7 , wherein generating the disparity signal includes performing an infinite impulse response filtering operation on at least a portion of the plurality of recovered data symbols.
10. The method of claim 7 , wherein generating the gain signal includes combining the disparity signal with information indicative of errors generated during the generation of the plurality of recovered data symbols.
11. The method of claim 10 , wherein adjusting the respective input voltage levels of the plurality of signals includes:
determining a differential voltage level using the gain signal; and
applying, based on the control signal, the differential voltage level to the plurality of signals.
12. The method of claim 7 , wherein generating the control signal includes:
performing a comparison of a running disparity and a plurality of threshold values, wherein the running disparity is based on the plurality of recovered data symbols; and
generating the control signal based on results of the comparison.
13. The method of claim 7 , wherein generating the gain signal includes:
performing a comparison of the disparity signal and a plurality of threshold values; and
multiplying, based on results of the comparison, information indicative of errors detected during the generation of the plurality of recovered data symbols by zero.
14. An apparatus, comprising:
a first device configured to transmit a plurality of signals that encodes a serial data stream that includes a plurality of data symbols; and
a second device configured to:
receive the plurality of signals;
generate an equalized signal using the plurality of signals;
sample, using a recovered clock signal, the equalized signal to generate a plurality of samples;
generate the recovered clock signal and a plurality of recovered data symbols using the plurality of samples;
generate a disparity signal using the recovered data symbols, wherein the disparity signal is indicative of a difference in respective numbers of different logic values in the plurality of recovered data symbols;
generate a gain signal and a control signal using the disparity signal; and
adjust respective input voltage levels of the plurality of signals using the gain signal and the control signal.
15. The apparatus of claim 14 , wherein to generate the disparity signal, the second device is further configured to accumulate respective numbers of logic values included in the plurality of recovered data symbols.
16. The apparatus of claim 14 , wherein to generate the disparity signal, the second device is further configured to perform an infinite impulse response filtering operation on at least a portion of the plurality of recovered data symbols.
17. The apparatus of claim 14 , wherein to generate the gain signal, the second device is further configured to generate the gain signal using a combination of the disparity signal with errors associated with the plurality of recovered data symbols.
18. The apparatus of claim 17 , wherein to adjust the respective input voltage levels of the plurality of signals, the second device is further configured to:
determine a differential voltage level using the gain signal; and
apply, based on the control signal, the differential voltage level to the plurality of signals.
19. The apparatus of claim 14 , wherein to generate the control signal, the second device is further configured to:
perform a comparison of a running disparity and a plurality of threshold values, wherein the running disparity is based on the plurality of recovered data symbols; and
generate the control signal based on results of the comparison.
20. The apparatus of claim 14 , wherein to generate the gain signal, the second device is further configured to:
perform a comparison of the disparity signal and plurality of threshold values; and
multiply, based on results of the comparison, the information indicative of errors detected during the generation of the plurality of recovered data symbols by 1.