Gate induced drain leakage reduction in FinFETs
A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.
1. A semiconductor device comprising:
a fin structure;
a channel epitaxial wrap around layer present on each end of a channel portion of the fin structure, wherein the channel epitaxial wrap around layer is a continuous and conformal layer;
a gate structure including a gate dielectric having end portions in direct contact with the channel epitaxial wrap around layer at said each end of the channel portion, and a middle portion of the gate dielectric is in direct contact with the fin structure at a portion between said each end of the channel portion;
source and drain regions on portions of the fin structure that are on opposing sides of the channel portion; and
spacers separating the gate structure from source and drain regions.
2. The semiconductor device of claim 1 , wherein the channel epitaxial wrap around layer is composed of silicon doped with carbon (Si:C).
3. The semiconductor device of claim 1 , wherein the channel epitaxial wrap around layer is composed of silicon germanium (SiGe).
4. The semiconductor device of claim 1 , wherein the channel epitaxial wrap around layer is present on sidewall and upper surfaces of the fin structure within a gate opening for housing the gate structure.
5. The semiconductor device of claim 1 , wherein the channel epitaxial wrap around layer has a thickness of less than 5 nm.
6. The semiconductor device of claim 1 , wherein when the fin structure is composed of silicon (Si), and the source and drain regions are n-type doped, and the channel epitaxial wrap around layer is composed of silicon doped with carbon (Si:C).
7. The semiconductor device of claim 1 , wherein the fin structure is composed of silicon (Si), and the source and drain region are p-type, and the channel epitaxial wrap around layer is composed of silicon germanium (SiGe).
8. The semiconductor device of claim 1 , wherein the channel epitaxial wrap around layer reduces gate induced drain leakage (GIDL).
9. The semiconductor device of claim 1 , wherein the channel epitaxial wrap around layer is present directly on an exterior surface of the fin structure.
10. A semiconductor device comprising:
a fin structure;
a channel epitaxial wrap around layer present on each end of a channel portion of the fin structure, wherein an end portion of the channel epitaxial wrap around layer horizontally extends over edge faces of the fin structure leaving an exposed section of the fin structure in the channel portion;
a gate structure including a gate dielectric having end portions in direct contact with the channel epitaxial wrap around layer at said each end of the channel portion, and a middle portion of the gate dielectric is in direct contact with the fin structure at the exposed section of the fin structure in the channel portion; and
source and drain regions on portions of the fin structure that are on opposing sides of the channel portion.
11. The semiconductor device of claim 10 , wherein the channel epitaxial wrap around layer is composed of silicon doped with carbon (Si:C).
12. The semiconductor device of claim 10 , wherein the channel epitaxial wrap around layer is composed of silicon germanium (SiGe).
13. The semiconductor device of claim 10 , wherein the channel epitaxial wrap around layer is present on sidewall and upper surfaces of the fin structure within a gate opening for housing the gate structure.
14. The semiconductor device of claim 10 , wherein the channel epitaxial wrap around layer is a continuous and conformal layer.
15. The semiconductor device of claim 10 , wherein the channel epitaxial wrap around layer has a thickness of less than 5 nm.
16. The semiconductor device of claim 10 , wherein the channel epitaxial wrap around layer reduces gate induced drain leakage (GIDL).
17. A semiconductor device comprising:
a semiconductor pedestal;
a channel epitaxial wrap around layer present on each end of a channel portion of the semiconductor pedestal;
a gate structure including a gate dielectric having end portions in direct contact with the channel epitaxial wrap around layer at said each end of the channel portion, and a middle portion of the gate dielectric is in direct contact with the semiconductor pedestal at a portion between said each end of the channel portion, wherein the channel epitaxial wrap around layer is a continuous and conformal layer; and
source and drain regions on portions of the semiconductor pedestal that are on opposing sides of the channel portion.
18. The semiconductor device of claim 17 , wherein the channel epitaxial wrap around layer is composed of silicon doped with carbon (Si:C).
19. The semiconductor of claim 17 , wherein the channel epitaxial wrap around layer is composed of silicon germanium (SiGe).
20. The semiconductor device of claim 1 , wherein the is composed of a material having a lower threshold voltage that the channel portion of the fin structure.