Multi-diameter magnetic random-access memory pillar structure

1. A semiconductor structure comprising:

a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter;

a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter; and

an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter;

wherein at least one of: the first diameter is less than the second diameter; and

the second diameter is less than the third diameter.

2. The semiconductor structure of claim 1 , wherein the third diameter is greater than the second diameter, and wherein the second diameter is greater than the first diameter.

3. The semiconductor structure of claim 1 , further comprising a tunnel barrier layer of the magnetic random-access memory pillar structure disposed between the reference layer and the free layer, the tunnel barrier layer having the second diameter.

4. The semiconductor structure of claim 1 , further comprising a first encapsulation layer surrounding sidewalls of the reference layer and a second encapsulation layer surrounding sidewalls of the free layer.

5. The semiconductor structure of claim 4 , wherein the first encapsulation layer and the second encapsulation layer are a same material.

6. The semiconductor structure of claim 4 , wherein the first encapsulation layer comprises a first dielectric material and the second encapsulation layer comprises a second dielectric material different than the first dielectric material.

7. The semiconductor structure of claim 6 , wherein the first dielectric material comprises silicon nitride (SiN) and the second dielectric material comprises silicon carbonitride (SiCN).

8. The semiconductor structure of claim 1 , further comprising a first interlevel dielectric layer surrounding the reference layer and a second interlevel dielectric layer surrounding the free layer.

9. The semiconductor structure of claim 8 , further comprising a third interlevel dielectric layer surrounding sidewalls of the electrode layer and another interlevel dielectric nucleation layer disposed between the second interlevel dielectric layer and the third interlevel dielectric layer.

10. A semiconductor structure comprising:

a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter;

a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter;

an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter;

a first interlevel dielectric layer surrounding the reference layer;

a second interlevel dielectric layer surrounding the free layer; and

an interlevel dielectric nucleation layer disposed between the first interlevel dielectric layer and the second interlevel dielectric layer;

wherein at least two of the first diameter, the second diameter and the third diameter are different.

11. The semiconductor structure of claim 10 , wherein:

the first interlevel dielectric layer and the second interlevel dielectric layer comprises at least one of: a dielectric including silicon, carbon, oxygen and hydrogen (SiCOH); a dielectric including silicon, carbon, nitrogen and oxygen (SiCNO); and a dielectric including silicon, carbon, hydrogen, nitrogen and oxygen (SiCHNO); and

the interlevel dielectric nucleation layer comprises at least one of silicon oxycarbide (SiOC), silicon nitride (SiN) and silicon carbonitride (SiCN).

12. An integrated circuit, comprising:

one or more magnetic random-access memory devices, at least one of the one or more magnetic random-access memory devices comprising a magnetic random-access memory pillar comprising:

a reference layer having a first diameter;

a free layer having a second diameter disposed over the reference layer; and

an electrode layer having a third diameter disposed over the free layer;

wherein at least one of: the first diameter is less than the second diameter; and

the second diameter is less than the third diameter.

13. The integrated circuit of claim 12 , wherein the third diameter is greater than the second diameter, and wherein the second diameter is greater than the first diameter.

14. The integrated circuit of claim 12 , further comprising a first encapsulation layer surrounding sidewalls of the reference layer and a second encapsulation layer surrounding sidewalls of the free layer, wherein the first encapsulation layer comprises a first dielectric material and the second encapsulation layer comprises a second dielectric material different than the first dielectric material.

15. The integrated circuit of claim 12 , further comprising a first interlevel dielectric layer surrounding the reference layer, a second interlevel dielectric layer surrounding the free layer, a third interlevel dielectric layer surrounding the electrode layer, a first interlevel dielectric nucleation layer disposed between the first interlevel dielectric layer and the second interlevel dielectric layer, and a second interlevel dielectric nucleation layer disposed between the second interlevel dielectric layer and the third interlevel dielectric layer.

16. The integrated circuit of claim 12 , further comprising a tunnel barrier layer of the magnetic random-access memory pillar structure disposed between the reference layer and the free layer, the tunnel barrier layer having the second diameter.

17. The integrated circuit of claim 12 , further comprising a first encapsulation layer surrounding sidewalls of the reference layer and a second encapsulation layer surrounding sidewalls of the free layer.

18. The integrated circuit of claim 17 , wherein the first encapsulation layer and the second encapsulation layer are a same material.

19. The integrated circuit of claim 12 , further comprising a first interlevel dielectric layer surrounding the reference layer and a second interlevel dielectric layer surrounding the free layer.

20. The integrated circuit of claim 19 , further comprising an interlevel dielectric nucleation layer disposed between the first interlevel dielectric layer and the second interlevel dielectric layer.