Convergent fin and nanostructure transistor structure and method
A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.
1. A method, comprising:
forming a substrate;
forming a first semiconductor fin over the substrate extending in a first lateral direction;
stacking a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction;
forming an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction;
forming a first gate structure surrounding and covering the first semiconductor fin, and extending in a second lateral direction substantially perpendicular to the first lateral direction;
forming a second gate structure surrounding and covering the first vertical stack, and extending in the second lateral direction; and
forming a gate isolation feature extending vertically from an upper surface of the inactive fin to a level at or above upper surfaces of the first gate structure and the second gate structure, wherein forming the gate isolation feature includes:
forming a first portion extending in the first lateral direction and having a first thickness; and
forming a second portion extending in the first lateral direction from the first portion, and having a second thickness less than the first thickness.
2. The method of claim 1 , wherein the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first semiconductor fin.
3. The method of claim 1 , wherein the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first vertical stack.
4. The method of claim 1 , wherein the gate isolation feature is formed by a self-aligned process following formation of the inactive fin.
5. The method of claim 1 , further comprising:
forming a dielectric layer on the first portion of the gate isolation feature; and
forming a spacer layer on the dielectric layer.
6. The method of claim 5 , further comprising:
forming an interlayer dielectric over the second portion of the gate isolation feature.
7. The method of claim 1 , further comprising:
forming first and second source/drain features abutting opposite sides of the first semiconductor fin; and
forming third and fourth source/drain features abutting opposite sides of the first vertical stack.
8. The method of claim 7 , wherein:
the first and third source/drain features are separated by the inactive fin; and
the second and fourth source/drain features are separated by the inactive fin.
9. The method of claim 8 , wherein the first and second source/drain features have smaller dimensions than the third and fourth source/drain features along the second lateral direction.
10. A method, comprising:
forming a substrate;
forming a first semiconductor fin over the substrate extending in a first lateral direction;
stacking a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction;
forming an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction;
forming a first gate structure surrounding and covering the first semiconductor fin, and extending in a second lateral direction substantially perpendicular to the first lateral direction;
forming a second gate structure surrounding and covering the first vertical stack, and extending in the second lateral direction;
forming a gate isolation feature extending vertically from an upper surface of the inactive fin to a level at or above upper surfaces of the first gate structure and the second gate structure, wherein forming the gate isolation feature includes:
forming a first portion extending in the first lateral direction and having a first thickness; and
forming a second portion extending in the first lateral direction from the first portion, and having a second thickness less than the first thickness;
forming first and second source/drain features abutting opposite sides of the first semiconductor fin; and
forming third and fourth source/drain features abutting opposite sides of the first vertical stack.
11. The method of claim 10 , wherein the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first semiconductor fin, and the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first vertical stack.
12. The method of claim 10 , further comprising:
forming a dielectric layer on the first portion of the gate isolation feature; and
forming a spacer layer on the dielectric layer.
13. The method of claim 12 , further comprising:
forming an interlayer dielectric over the second portion of the gate isolation feature.
14. The method of claim 10 , wherein:
the first and third source/drain features are separated by the inactive fin; and
the second and fourth source/drain features are separated by the inactive fin.
15. The method of claim 14 , wherein the first and second source/drain features have smaller dimensions than the third and fourth source/drain features along the second lateral direction.
16. A method, comprising:
forming a substrate;
forming a first semiconductor fin over the substrate extending in a first lateral direction;
stacking a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction;
forming an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction, the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first semiconductor fin, and the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first vertical stack;
forming a first gate structure surrounding and covering the first semiconductor fin, extending in a second lateral direction substantially perpendicular to the first lateral direction;
forming a second gate structure surrounding and covering the first vertical stack, and extending in the second lateral direction; and
forming a gate isolation feature extending vertically from an upper surface of the inactive fin to a level at or above upper surfaces of the first gate structure and the second gate structure, wherein forming the gate isolation feature includes:
forming a first portion extending in the first lateral direction and having a first thickness; and
forming a second portion extending in the first lateral direction from the first portion, and having a second thickness less than the first thickness.
17. The method of claim 16 , wherein the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first semiconductor fin, and the inactive fin protrudes 5 nm to 25 nm above an upper surface of the first vertical stack.
18. The method of claim 16 , further comprising:
forming a dielectric layer on the first portion of the gate isolation feature; and
forming a spacer layer on the dielectric layer.
19. The method of claim 18 , further comprising:
forming an interlayer dielectric over the second portion of the gate isolation feature.
20. The method of claim 16 , further comprising:
forming first and second source/drain features abutting opposite sides of the first semiconductor fin; and
forming third and fourth source/drain features abutting opposite sides of the first vertical stack.