IP Library › Granted Patent US 12,261,259
Granted Patent B2
US 12,261,259 · App. 17/481,326 · Granted Mar 25, 2025

Light-emitting chip and light-emitting substrate

Inventors: Linxia Qi (Beijing, CN); Junjie Ma (Beijing, CN); Yuanda Lu (Beijing, CN); Shanwei Yang (Beijing, CN); Jiawei Zhao (Beijing, CN); Zhijun Xiong (Beijing, CN); Haiwei Sun (Beijing, CN); Lingyun Shi (Beijing, CN); Jinpeng Li (Beijing, CN)
Assignees: BOE MLED Technology Co., Ltd.; BOE Technology Group Co., Ltd.
H01L33/62H01L25/0753H01L33/382
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Quick Facts
Patent No.
US 12,261,259
App. No.
17/481,326
Granted
Mar 25, 2025
Kind
B2
Abstract

A light-emitting chip and a light-emitting substrate are provided. The light-emitting chip includes a base substrate and at least two sub-light-emitting chips disposed on a side of the base substrate, wherein each sub-light-emitting chip includes a first semiconductor layer, a second semiconductor layer and an light-emitting layer located between the first semiconductor layer and the second semiconductor layer which are stacked.

Claims (14)

1. A light-emitting chip, comprising: a base substrate and at least two sub-light-emitting chips disposed on a side of the base substrate, wherein each sub-light-emitting chip comprises a first semiconductor layer, a second semiconductor layer and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, which are stacked;

wherein the at least two sub-light-emitting chips are connected in series to form a series group of sub-light-emitting chips, and the light-emitting chip further comprises a first electrode and a second electrode, the first electrode is connected to a sub-light-emitting chip at a first terminal of the series group of sub-light-emitting chips and the second electrode is connected to a sub-light-emitting chip at a second terminal of the series group of sub-light-emitting chips;

wherein in a direction perpendicular to the base substrate, the first electrode and the second electrode are located on a side of the second semiconductor layer away from the light-emitting layer, and a second insulating layer is disposed between the first and second electrodes and the second semiconductor layer; the second insulating layer is provided with a first via hole exposing a sub-light-emitting chip at the first terminal of the series group of sub-light-emitting chips and a second via hole exposing a sub-light-emitting chip at the second terminal of the series group of sub-light-emitting chips; the first electrode is connected to the sub-light-emitting chip at the first terminal of the series group of sub-light-emitting chips through the first via hole, and the second electrode is connected to the sub-light-emitting chip at the second terminal of the series group of sub-light-emitting chips through the second via hole.

2. The light-emitting chip according to claim 1 , wherein a vertical projection of any one of the sub-light-emitting chips in the series group of sub-light-emitting chips on the base substrate overlaps with a vertical projection of at least one of the first electrode and the second electrode on the base substrate.

3. The light-emitting chip according to claim 1 , wherein in a direction parallel to the base substrate, the sub-light-emitting chips in the series group of sub-light-emitting chips are arranged side by side along a first direction of the base substrate; or, the sub-light-emitting chips are arranged in a triangle; or, the sub-light-emitting chips are disposed in a rectangle.

4. The light-emitting chip according to claim 1 , further comprising a series electrode disposed on a side of the base substrate, wherein a first terminal of the series electrode is connected to the first semiconductor layer of one of adjacent sub-light-emitting chips, and a second terminal of the series electrode is connected to the second semiconductor layer of the other one of the adjacent sub-light-emitting chips.

5. The light-emitting chip according to claim 4 , wherein in a direction perpendicular to the base substrate, a first insulating layer is disposed between the first terminal of the series electrode and the second semiconductor layer of one of the adjacent sub-light-emitting chips; and/or the first insulating layer is disposed between the second terminal of the series electrode and the first semiconductor layer of the other one of the adjacent sub-light-emitting chips.

6. The light-emitting chip according to claim 1 , wherein the second insulating layer is made of a reflective material.

7. The light-emitting chip according to claim 1 , wherein the sub-light-emitting chips are rectangular or triangular.

8. A light-emitting substrate, comprising: a drive back plate and a light-emitting chip disposed on a side of the drive back plate, wherein the light-emitting chip is the light-emitting chip according to claim 1 .

9. The light-emitting substrate according to claim 8 , wherein a vertical projection of any one of the sub-light-emitting chips in the series group of sub-light-emitting chips on the base substrate overlaps with a vertical projection of at least one of the first electrode and the second electrode on the base substrate.

10. The light-emitting substrate according to claim 8 , wherein in a direction parallel to the base substrate, the sub-light-emitting chips in the series group of sub-light-emitting chips are arranged side by side along a first direction of the base substrate; or, the sub-light-emitting chips are arranged in a triangle; or, the sub-light-emitting chips are disposed in a rectangle.

11. The light-emitting substrate according to claim 8 , further comprising a series electrode disposed on a side of the base substrate, wherein a first terminal of the series electrode is connected to the first semiconductor layer of one of adjacent sub-light-emitting chips, and a second terminal of the series electrode is connected to the second semiconductor layer of the other one of the adjacent sub-light-emitting chips.

12. The light-emitting substrate according to claim 8 , wherein in a direction perpendicular to the base substrate, the first electrode and the second electrode are located on a side of the second semiconductor layer away from the light-emitting layer, and a second insulating layer is disposed between the first and second electrodes and the second semiconductor layer; the second insulating layer is provided with a first via hole exposing the sub-light-emitting chip at the first terminal of the series group of sub-light-emitting chips and a second via hole exposing the sub-light-emitting chip at the second terminal of the series group of sub-light-emitting chips; the first electrode is connected to the sub-light-emitting chip at the first terminal of the series group of sub-light-emitting chips through the first via hole, and the second electrode is connected to the sub-light-emitting chip at the second terminal of the series group of sub-light-emitting chips through the second via hole.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2022
From: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
To: BOE MLED TECHNOLOGY CO., LTD.
Reel/Frame 059274/0926 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2021
From: QI, LINXIA; MA, JUNJIE; LU, YUANDA; YANG, SHANWEI; ZHAO, JIAWEI; XIONG, ZHIJUN; SUN, HAIWEI; SHI, LINGYUN; LI, JINPENG
To: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 057602/0924 →
Priority Claims (1)
CN 202110178736.8 · Feb 7, 2021 · national
Continuity (1)
Related Publication 20220254969A1 · Aug 11, 2022
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