Gathering payload from arbitrary registers for send messages in a graphics environment
An apparatus to facilitate gathering payload from arbitrary registers for send messages in a graphics environment is disclosed. The apparatus includes processing resources comprising execution circuitry to receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers; decode a first phase of the send gather message instruction; based on decoding the first phase, cause a second phase of the send gather message instruction to bypass an instruction decode stage; and dispatch the first phase subsequently followed by dispatch of the second phase to a send pipeline. The apparatus can also perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry and include a pointer to the architectural register in the send gather message instruction.
1. A processor comprising:
processing resources comprising execution circuitry to:
receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers;
decode a first phase of the send gather message instruction;
based on decoding the first phase of the send gather message instruction, cause a second phase of the send gather message instruction to bypass an instruction decode stage of the execution circuitry; and
dispatch the first phase of the send gather message instruction subsequently followed by dispatch of the second phase of the send gather message instruction to a send pipeline of the execution circuitry.
2. The processor of claim 1 , wherein the dispatch of the first phase and the second phase of the send gather message instruction are dispatched to the send pipeline without any intervening dispatched messages between the first phase and the second phase in the send pipeline.
3. The processor of claim 1 , wherein the plurality of individual registers comprise general register file (GRF) registers.
4. The processor of claim 1 , wherein the second phase of the send gather message instruction comprises the IDs of the plurality of individual registers.
5. The processor of claim 1 , wherein the first phase of the send gather message instruction identifies the number of the registers to access for the send message.
6. The processor of claim 1 , wherein the plurality of individual registers are non-contiguous.
7. The processor of claim 1 , wherein the first phase of the send gather message instruction identifies a destination shared function ID, a function-specific encoding of an operation of the send gather message instruction, and a destination register for a writeback response to the send gather message instruction.
8. The processor of claim 1 , wherein the processor comprises a graphics processing unit (GPU).
9. The processor of claim 1 , wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.
10. A method comprising:
receiving, by execution circuitry of a graphics processor, a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers;
decoding a first phase of the send gather message instruction;
based on decoding the first phase of the send gather message instruction, causing a second phase of the send gather message instruction to bypass an instruction decode stage of the execution circuitry; and
dispatching the first phase of the send gather message instruction subsequently followed by dispatch of the second phase of the send gather message instruction to a send pipeline of the execution circuitry.
11. The method of claim 10 , wherein the dispatch of the first phase and the second phase of the send gather message instruction are dispatched to the send pipeline without any intervening dispatched messages between the first phase and the second phase in the send pipeline.
12. The method of claim 10 , wherein the plurality of individual registers comprise general register file (GRF) registers.
13. The method of claim 10 , wherein the first phase of the send gather message instruction identifies the number of the registers to access for the send message, and wherein the second phase of the send gather message instruction comprises the IDs of the plurality of individual registers.
14. The method of claim 10 , wherein the plurality of individual registers are non-contiguous.
15. The method of claim 10 , wherein the first phase of the send gather message instruction identifies a destination shared function ID, a function-specific encoding of an operation of the send gather message instruction, and a destination register for a writeback response to the send gather message instruction.
16. A system comprising:
a memory to store a block of data; and
a processor coupled to the memory, the processor comprising processing resources, the processing resources comprising execution circuitry to:
receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers;
decode a first phase of the send gather message instruction;
based on decoding the first phase of the send gather message instruction, cause a second phase of the send gather message instruction to bypass an instruction decode stage of the execution circuitry; and
dispatch the first phase of the send gather message instruction subsequently followed by dispatch of the second phase of the send gather message instruction to a send pipeline of the execution circuitry.
17. The system of claim 16 , wherein the execution circuitry is further to:
perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry;
include a pointer to the architectural register in the send gather message instruction; and
dispatch the send gather message instruction to a send pipeline of the execution circuitry;
wherein the architectural register is a scalar register.
18. The system of claim 17 , wherein the send gather message instruction identifies the number of the registers to access for the send gather message instruction and the architectural register.
19. The system of claim 16 , wherein the plurality of individual registers are non-contiguous, and wherein the IDs comprise pointers.
20. The system of claim 16 , wherein the send gather message instruction identifies a destination shared function ID, a function-specific encoding of an operation of the send gather message instruction, and a destination register for a writeback response to the send gather message instruction.