Backside electrical contacts to buried power rails
A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.
1. A method comprising:
arranging a multi-layer stack on a semiconductor substrate, wherein the multi-layer stack comprises a nanosheet stack arranged above a dielectric isolation layer;
arranging a plurality of dummy gates above the nanosheet stack;
etching through the nanosheet stack between the plurality of dummy gates to form one or more trenches;
depositing semiconductor material in the one or more trenches to form a source/drain region, wherein the source/drain region comprises a top surface and a bottom surface positioned between the top surface and the semiconductor substrate;
removing a portion of the semiconductor substrate such that the bottom surface of the source/drain region is exposed;
forming an electrical contact that extends through one or more layers to the bottom surface; and
forming a buried power rail that contacts the bottom surface through the electrical contact.
2. The method of claim 1 , wherein the nanosheet stack comprises an alternating arrangement of silicon layers and silicon germanium layers.
3. The method of claim 1 , further comprising:
performing one or more additional front end of line (FEOL) processes and one or more back end of line (BEOL) processes after forming the source/drain region;
bonding a carrier wafer to a top surface defined by the one or more BEOL processes; and
inverting the carrier wafer before exposing the bottom surface.
4. The method of claim 1 , wherein the one or more layers comprise the semiconductor substrate.
5. The method of claim 1 , wherein forming the buried power rail comprises:
arranging an interlayer dielectric (ILD) layer below a bottom surface of the electrical contact; and
etching through the ILD layer to the bottom surface of the electrical contact.
6. The method of claim 1 , further comprising:
etching through the dielectric isolation layer and partly through the semiconductor substrate to form the one or more trenches.
7. The method of claim 6 , further comprising:
depositing a sacrificial material in the one or more trenches,
wherein the semiconductor material is disposed above the sacrificial material.
8. The method of claim 7 , wherein exposing the bottom surface comprises:
selectively etching the sacrificial material.
9. The method of claim 7 , further comprising:
depositing a semiconductor buffer above the sacrificial material,
wherein the semiconductor material contacts the semiconductor buffer.
10. The method of claim 1 ,
wherein the semiconductor substrate is a silicon substrate of a silicon-on-insulator (SOI) wafer, and
wherein the dielectric isolation layer is a buried oxide (BOX) layer of the SOI wafer,
the method further comprising:
etching at least partly through the BOX layer to form the one or more trenches.
11. The method of claim 1 , wherein the multi-layer stack further comprises a silicon layer between the nanosheet stack and the dielectric isolation layer, the method further comprising:
etching partly through the silicon layer to form the one or more trenches.
12. The method of claim 11 , wherein exposing the bottom surface comprises:
removing the semiconductor substrate;
removing the dielectric isolation layer; and
removing the silicon layer.
13. A method comprising:
arranging a nanosheet stack above a silicon substrate;
arranging a plurality of dummy gates above the nanosheet stack;
forming one or more contact placeholders between the plurality of dummy gates, wherein forming the one or more contact placeholders comprises etching through the nanosheet stack;
forming a source/drain region above the one or more contact placeholders, wherein the source/drain region comprises a top surface and a bottom surface positioned between the top surface and the silicon substrate;
etching at least partly through the silicon substrate to the one or more contact placeholders; and
selectively etching the one or more contact placeholders to expose the bottom surface of the source/drain region; and
forming an electrical contact that extends through one or more layers to the bottom surface.
14. The method of claim 13 , wherein the one or more contact placeholders comprise a sacrificial dielectric material.
15. The method of claim 13 , wherein the one or more contact placeholders comprise a sacrificial silicon germanium material.
16. The method of claim 15 , further comprising:
depositing one or more silicon buffers above the one or more contact placeholders,
wherein the source/drain region contacts the one or more silicon buffers.