Latency reduction in analog-to-digital converter-based receiver circuits

1. An apparatus, comprising:

a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;

a sample circuit including a plurality of analog-to-digital converter circuits, wherein an activated subset of the plurality of analog-to-digital converter circuits are configured to sample, using a recovered clock signal, the equalized signal during respective time periods to generate corresponding sets of samples, wherein a number of analog-to-digital converter circuits included in the activated subset is based on a baud rate of the serial data stream, wherein the sample circuit is configured to generate a plurality of serialized sample streams that include samples from respective subsets of the activated subset of the plurality of analog-to-digital converter circuits, wherein a first serialized sample stream of the plurality of serialized sample streams includes first data corresponding to even-numbered data symbols of the plurality of data symbols, and wherein a second serialized sample stream of the plurality of serialized sample streams includes second data corresponding to odd-numbered data symbols of the plurality of data symbols; and

a recovery circuit configured to generate, using the corresponding sets of samples, the recovered clock signal and a plurality of recovered data symbols.

2. The apparatus of claim 1 , wherein the plurality of analog-to-digital converter circuits are further configured to sample, using respective ones of a plurality of sample clock signals, the equalized signal to generate the corresponding sets of samples, wherein the plurality of sample clock signals are based on the recovered clock signal, and wherein a given sample included in a particular set of samples is aligned with a corresponding one of the plurality of sample clock signals.

3. The apparatus of claim 2 , wherein the sample circuit is further configured to generate the plurality of sample clock signals using the recovered clock signal.

4. The apparatus of claim 3 , further comprising a re-timer circuit configured to generate a plurality of re-timed samples using the corresponding sets of samples and a different clock signal, wherein a frequency of the different clock signal is different than respective frequencies of the plurality of sample clock signals.

5. The apparatus of claim 1 , wherein the sample circuit further includes a plurality of buffer circuits configured to sample, based on corresponding ones of a plurality of buffer clock signals, the equalized signal to generate a corresponding plurality of buffered samples, and wherein the subset of the plurality of analog-to-digital converter circuits are configured to quantize respective ones of the corresponding plurality of buffered samples to generate the corresponding sets of samples.

6. The apparatus of claim 1 , wherein to generate the equalized signal, the front-end circuit is further configured to:

filter the plurality of signals to generate a filtered signal; and

adjust a magnitude of the filtered signal to generate the equalized signal.

7. A method, comprising:

generating an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;

sampling, by an activated subset of a plurality of analog-to-digital converter circuits using a recovered clock signal, the equalized signal during respective time periods to generate corresponding sets of samples, wherein a number of analog-to-digital converter circuits included in the activated subset is based on a baud rate of the serial data stream;

generating a plurality of serialized sample streams that include samples from respective subsets of the activated subset of the plurality of analog-to-digital converter circuits, wherein a first serialized sample stream of the plurality of serialized sample streams includes first data corresponding to even-numbered data symbols of the plurality of data symbols, and wherein a second serialized sample stream of the plurality of serialized sample streams includes second data corresponding to odd-numbered data symbols of the plurality of data symbols; and

generating, using the plurality of serialized sample streams, the recovered clock signal and a plurality of recovered data symbols.

8. The method of claim 7 , wherein sampling the equalized signal includes sampling, using respective ones of a plurality of sample clock signals, the equalized signal to generate the corresponding sets of samples, wherein the plurality of sample clock signals are based on the recovered clock signal, and wherein a given sample included in a particular set of the corresponding sets of samples is aligned with a corresponding one of the plurality of sample clock signals.

9. The method of claim 8 , further comprising, generating the plurality of sample clock signals using the recovered clock signal.

10. The method of claim 9 , further comprising, generating a plurality of re-timed samples using the corresponding sets of samples and a different clock signal, wherein a frequency of the different clock signal is different than respective frequencies of the plurality of sample clock signals.

11. The method of claim 10 , wherein sampling the equalized signal includes:

sampling, by a plurality of buffer circuits using corresponding ones of a plurality of buffer clock signals, the equalized signal to generate a corresponding plurality of buffered samples; and

quantizing, by the subset of the plurality of analog-to-digital converters circuits, respective ones of the corresponding plurality of buffered samples to generate the corresponding sets of samples.

12. The method of claim 10 , wherein generating the plurality of recovered data symbols includes performing a feed-forward equalization operation using the corresponding sets of samples.

13. The method of claim 7 , wherein generating the equalized signal includes:

filtering the plurality of signals to generate a filtered signal; and

adjusting a magnitude of the filtered signal to generate the equalized signal.

14. An apparatus, comprising:

a front-end circuit configured to generate an equalized signal using at least one signal that encodes a serial data stream that includes a plurality of data symbols;

a sample circuit configured to:

sample, using a recovered clock signal, the equalized signal to generate a plurality of samples; and

re-time the plurality of samples to align a plurality of subsets of the plurality of samples with corresponding sample clock phases of a plurality of sample clock phases;

a serializer circuit configured to generate a plurality of serialized sample streams that include respective ones of the plurality of subsets of the plurality of samples, wherein a first serialized sample stream of the plurality of serialized sample streams includes first data corresponding to even-numbered data symbols of the plurality of data symbols, and wherein a second serialized sample stream of the plurality of serialized sample streams includes second data corresponding to odd-numbered data symbols of the plurality of data symbols; and

a recovery circuit configured to generate, using the plurality of serialized sample streams, the recovered clock signal and a plurality of recovered data symbols.

15. The apparatus of claim 14 , wherein the sample circuit includes a plurality of analog-to-digital converters circuits configured to sample, using a plurality of sample clock phases, the equalized signal during respective time periods, wherein a given analog-to-digital converter circuit of the plurality of analog-to-digital converters circuits is configured to generate a corresponding subset of the plurality of subsets of the plurality of samples.

16. The apparatus of claim 15 , wherein the sample circuit is further configured to generate the plurality of sample clock phases using the recovered clock signal.

17. The apparatus of claim 14 , wherein a number of serialized symbol streams is based on a baud rate of the serial data stream.

18. The apparatus of claim 14 , wherein to generate the equalized signal, the front-end circuit is further configured to:

filter the at least one signal to generate a filtered signal; and

adjust a magnitude of the filtered signal to generate the equalized signal.

19. The apparatus of claim 14 , wherein to generate the plurality of recovered data symbols, the recovery circuit is further configured to perform a feed-forward equalization operation using the plurality of serialized sample streams.