Switched capacitor multiplier for compute in-memory applications

1. A computing system comprising:

a memory array to store a first digital number and a second digital number;

a plurality of capacitors coupled with the memory array, wherein each of the plurality of capacitors includes a first plate and a second plate;

a plurality of switches that selectively couple the plurality of capacitors to a plurality of voltages; and

logic that is connected to the plurality of switches, wherein the logic is to:

identify whether a product of the first digital number and the second digital number is associated with a positive value or a negative value;

during a first clock phase, set a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value;

during the first clock phase, control the plurality of switches to supply the first reference voltage to the first plates of the plurality of capacitors; and

during the first clock phase, control the plurality of switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.

2. The computing system of claim 1 , wherein the logic is to control the plurality of switches during a second clock phase to:

electrically connect the first plates to an output; and

electrically connect the second plates to the second reference voltage.

3. The computing system of claim 2 , wherein the logic is to:

determine that a first capacitor of the plurality of capacitors is associated with a low value of the second digital number; and

control the plurality of switches during a third clock phase to:

electrically connect the first plates to a third reference voltage, and

electrically connect the second plate of the first capacitor to the second reference voltage based on the first capacitor being associated with the low value.

4. The computing system of claim 3 , wherein the logic is to:

determine that a second capacitor of the plurality of capacitors is associated with a high value of the second digital number; and

during the third clock phase, control the plurality of switches to electrically disconnect the second plate of the second capacitor from the second reference voltage based on the second capacitor being associated with the high value.

5. The computing system of claim 4 , wherein the logic is to control the plurality of switches during a fourth clock phase to:

electrically connect the first plates to an output; and

electrically connect the second plates to the second reference voltage.

6. The computing system of claim 1 , wherein:

the second reference voltage is a ground voltage;

the first digital number is an input associated with a neural network; and

the second digital number is a weight associated with the neural network.

7. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:

identify whether a product of a first digital number and a second digital number is associated with a positive value or a negative value;

during a first clock phase, set a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value;

during the first clock phase, control a plurality of switches to supply the first reference voltage to first plates of a plurality of capacitors, wherein each of the plurality of capacitors includes a respective first plate of the first plates and a second plate; and

during the first clock phase, control the plurality of switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.

8. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to control the plurality of switches during a second clock phase to:

electrically connect the first plates to an output; and

electrically connect the second plates to the second reference voltage.

9. The apparatus of claim 8 , wherein the logic coupled to the one or more substrates is to:

determine that a first capacitor of the plurality of capacitors is associated with a low value of the second digital number; and

control the plurality of switches during a third clock phase to:

electrically connect the first plates to a third reference voltage, and

electrically connect the second plate of the first capacitor to the second reference voltage based on the first capacitor being associated with the low value.

10. The apparatus of claim 9 , wherein the logic coupled to the one or more substrates is to:

determine that a second capacitor of the plurality of capacitors is associated with a high value of the second digital number; and

during the third clock phase, control the plurality of switches to electrically disconnect the second plate of the second capacitor from the second reference voltage based on the second capacitor being associated with the high value.

11. The apparatus of claim 10 , wherein the logic coupled to the one or more substrates is to control the plurality of switches during a fourth clock phase to:

electrically connect the first plates to an output; and

electrically connect the second plates to the second reference voltage.

12. The apparatus of claim 7 , wherein:

the second reference voltage is a ground voltage;

the first digital number is an input associated with a neural network; and

the second digital number is a weight associated with the neural network.

13. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

14. A method comprising:

identifying whether a product of a first digital number and a second digital number is associated with a positive value or a negative value;

during a first clock phase, setting a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value;

during the first clock phase, controlling a plurality of switches to supply the first reference voltage to first plates of a plurality of capacitors, wherein each of the plurality of capacitors includes a respective first plate of the first plates and a second plate; and

during the first clock phase, controlling the plurality of switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.

15. The method of claim 14 , further comprising controlling the plurality of switches during a second clock phase to:

electrically connect the first plates to an output; and

electrically connect the second plates to the second reference voltage.

16. The method of claim 15 , further comprising:

determining that a first capacitor of the plurality of capacitors is associated with a low value of the second digital number; and

controlling the plurality of switches during a third clock phase to:

electrically connect the first plates to a third reference voltage, and

electrically connect the second plate of the first capacitor to the second reference voltage based on the first capacitor being associated with the low value.

17. The method of claim 16 , further comprising:

determining that a second capacitor of the plurality of capacitors is associated with a high value of the second digital number; and

during the third clock phase, controlling the plurality of switches to electrically disconnect the second plate of the second capacitor from the second reference voltage based on the second capacitor being associated with the high value.

18. The method of claim 17 , further comprising controlling the plurality of switches during a fourth clock phase to:

electrically connecting the first plates to an output; and

electrically connecting the second plates to the second reference voltage.

19. The method of claim 14 , wherein:

the second reference voltage is a ground voltage;

the first digital number is an input associated with a neural network; and

the second digital number is a weight associated with the neural network.

20. At least one computer readable storage medium comprising a set of instructions which, when executed by a computing system, cause the computing system to:

identify whether a product of a first digital number and a second digital number is associated with a positive value or a negative value;

during a first clock phase, set a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value;

during the first clock phase, control a plurality of switches to supply the first reference voltage to first plates of a plurality of capacitors, wherein each of the plurality of capacitors includes a respective first plate of the first plates and a second plate; and

during the first clock phase, control the plurality of switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.

21. The at least one computer readable storage medium of claim 20 , wherein the set of instructions, when executed, cause the computing system to:

electrically connect the first plates to an output; and

electrically connect the second plates to the second reference voltage.

22. The at least one computer readable storage medium of claim 21 , wherein the set of instructions, when executed, cause the computing system to:

determine that a first capacitor of the plurality of capacitors is associated with a low value of the second digital number; and

control the plurality of switches during a third clock phase to:

electrically connect the first plates to a third reference voltage, and

electrically connect the second plate of the first capacitor to the second reference voltage based on the first capacitor being associated with the low value.

23. The at least one computer readable storage medium of claim 22 , wherein the set of instructions, when executed, cause the computing system to:

determine that a second capacitor of the plurality of capacitors is associated with a high value of the second digital number; and

during the third clock phase, control the plurality of switches to electrically disconnect the second plate of the second capacitor from the second reference voltage based on the second capacitor being associated with the high value.

24. The at least one computer readable storage medium of claim 23 , wherein the set of instructions, when executed, cause the computing system to:

electrically connect the first plates to an output; and

electrically connect the second plates to the second reference voltage.

25. The at least one computer readable storage medium of claim 20 , wherein

the second reference voltage is a ground voltage;

the first digital number is an input associated with a neural network; and

the second digital number is a weight associated with the neural network.