Data loading and storage system and method
View Patent ↗A data loading and storage system includes a storage module, a buffering module, a control module, a plurality of data loading modules, a plurality of data storage modules and a multi-core processor array module. The data is continuously stored in a DDR, and the data computed by the multi-core processor may be arranged continuously or be arranged according to a certain rule. After DMA reads the data into the DATA_BUF module by a BURST mode, in order to support fast loading of the data into the multi-core processor array, the data loading modules (i.e., load modules) are designed. In order to quickly store the computed result of the multi-core processor array into the (DATA_BUF module according to a certain rule, the data storage modules (i.e., store module) are designed.
1. A data loading and storage system, comprising:
a storage module, configured to store configuration instructions and data;
a buffering module, comprising an instruction buffering module and a data buffering module, wherein the instruction buffering module is configured to buffer the configuration instructions in the storage module, and the data buffering module is configured to buffer the data in the storage module;
a control module, configured to send a trigger signal;
a plurality of data loading modules, configured to read the configuration instructions in the instruction buffering module in response to receiving the trigger signal, generate a data address according to the configuration instructions, and read the data in the data buffering module according to the data address;
a multi-core processor array module, configured to receive the data read by the plurality of data loading modules, and compute the received data to obtain computed data; and
a plurality of data storage modules, configured to receive and store the computed data from the multi-core processor array module;
wherein the data buffering module is further configured to receive and buffer the computed data from the multi-core processor array module, and write the computed data back to the storage module,
the plurality of data loading modules and the plurality of data storage modules are each provided with a fast Fourier transform (FFT) dedicated address generator; and
the plurality of data loading modules are configured to load the data and a twiddle factor from the plurality of data buffering modules, and the FFT dedicated address generator is configured to generate addresses according to a number of points and a current level of FFT in response to calling the FFT dedicated address generator.
2. The data loading and storage system according to claim 1 , wherein the plurality of data loading modules and the plurality of data storage modules are respectively provided with a plurality of corresponding fetching modules configured to generate addresses for reading the configuration instructions.
3. The data loading and storage system according to claim 2 , wherein the plurality of data loading modules and the plurality of data storage modules are respectively provided with a plurality of corresponding decoding modules configured to receive the configuration instructions output by the fetching modules;
wherein the plurality of decoding modules are further configured to analyze and store parameters of the configuration instructions.
4. The data loading and storage system according to claim 3 , wherein the plurality of data loading modules and the plurality of data storage modules are respectively provided with a plurality of corresponding address generating modules configured to receive the parameters of the configuration instructions output by the decoding modules.
5. The data loading and storage system according to claim 4 , wherein the plurality of address generating modules are configured to perform indirect addressing or direct addressing according to the configuration instructions.
6. The data loading and storage system according to claim 5 , further comprising a plurality of registers, wherein a register used for a base address is selected from the plurality of registers according to a parameter of a corresponding field of the configuration instructions in response to the indirect addressing of the plurality of address generating modules.
7. The data loading and storage system according to claim 6 , wherein the address generating module is configured to support address conversion, address modulo and normal mode.
8. The data loading and storage system according to claim 7 , wherein a number of the plurality of data loading modules and a number of the plurality of data storage modules are determined according to a specification of the multi-core processor array module.
9. The data loading and storage system according to claim 1 , wherein the plurality of data storage modules are configured to store the computed data from the multi-core processor array module into the plurality of data buffering modules for next-level FFT computing.
10. A data loading and storage method, comprising:
storing configuration instructions and data;
buffering the configuration instructions and the data;
reading the configuration instructions in response to receiving a trigger signal, generating a data address according to the configuration instructions, and reading the data according to the data address;
receiving the read data, and computing the received data to obtain computed data;
receiving and storing the computed data; and
receiving and buffering the computed data, and storing the computed data again,
wherein the method further comprises: generating a fast Fourier transform (FFT) dedicated address.
11. The data loading and storage method according to claim 10 , further comprising:
reading addresses of the configuration instructions.
12. The data loading and storage method according to claim 11 , further comprising:
receiving the configuration instructions, and analyzing and storing parameters of the configuration instructions.
13. The data loading and storage method according to claim 12 , further comprising:
performing indirect addressing or direct addressing according to the configuration instructions.
14. The data loading and storage method according to claim 13 , further comprising:
selecting a register for a base address according to a parameter of a corresponding field of the configuration instructions in response to the indirect addressing.
15. The data loading and storage method according to claim 14 , further comprising:
supporting address conversion, address modulo and normal mode.
16. The data loading and storage method according to claim 11 , further comprising:
loading the data and a twiddle factor; and
generating the FFT dedicated address according to a number of points and a current level of FFT.
17. The data loading and storage method according to claim 16 , further comprising:
storing the computed data for next-level FFT computing.
18. A data loading and storage system, comprising:
a storage module, configured to store configuration instructions and data;
a buffering module, comprising an instruction buffering module and a data buffering module, wherein the instruction buffering module is configured to buffer the configuration instructions in the storage module, and the data buffering module is configured to buffer the data in the storage module;
a control module, configured to send a trigger signal;
a plurality of data loading modules, configured to read the configuration instructions in the instruction buffering module in response to receiving the trigger signal, generate a data address according to the configuration instructions, and read the data in the data buffering module according to the data address;
a multi-core processor array module, configured to receive the data read by the plurality of data loading modules, and compute the received data to obtain computed data; and
a plurality of data storage modules, configured to receive and store the computed data from the multi-core processor array module;
wherein the data buffering module is further configured to receive and buffer the computed data from the multi-core processor array module, and write the computed data back to the storage module,
wherein a number of the plurality of data loading modules and a number of the plurality of data storage modules are determined according to a specification of the multi-core processor array module.
19. The data loading and storage system according to claim 18 , wherein the plurality of data loading modules and the plurality of data storage modules are respectively provided with a plurality of corresponding fetching modules configured to generate addresses for reading the configuration instructions.
20. The data loading and storage system according to claim 19 , wherein the plurality of data loading modules and the plurality of data storage modules are respectively provided with a plurality of corresponding decoding modules configured to receive the configuration instructions output by the fetching modules;
wherein the plurality of decoding modules are further configured to analyze and store parameters of the configuration instructions.