Method of routing in a singular direction first traces that are electrically coupled to respective rows of an array of touch sensors between respective second traces that are electrically coupled to respective columns of the array
A method for improving flexibility of a circuit board, e.g., comprising a touch-based sensor, and reducing manufacturing costs by eliminating routing around a border of the touch-based sensor is presented herein. The method comprises forming an array of touch sensors on a first side of the circuit board, in which portions of the circuit board located between three edges of the circuit board and a border of the array of touch sensors exclude traces; and forming first traces between respective second traces in a singular direction on a second side of the circuit board, in which the first traces are electrically coupled, using a first group of vias, to respective rows of the array of touch sensors, and the second traces are electrically coupled, using a second group of vias, to respective columns of the array of touch sensors.
1. A method, comprising:
forming an array of sensors on a first side of a circuit board; and
alternately forming first traces between second traces in a singular direction on a second side of the circuit board, wherein the first traces are electrically coupled, using a first group of vias, to respective rows of the array of sensors, and wherein the second traces are electrically coupled, using a second group of vias, to respective columns of the array of sensors.
2. The method of claim 1 , further comprising:
embedding resistors between respective traces of the first traces.
3. The method of claim 2 , wherein the embedding comprises:
printing, via respective thick-film carbon depositions, the resistors between the respective traces of the first traces.
4. The method of claim 1 , further comprising:
embedding resistors between respective traces of the second traces.
5. The method of claim 4 , wherein the embedding comprises:
printing, via respective thick-film carbon depositions, the resistors between the respective traces of the second traces.
6. The method of claim 1 , further comprising:
attaching, to a tail portion of the circuit board, surface mount resistors; and
electrically connecting the surface mount resistors to respective traces of at least one of the first traces or the second traces.
7. The method of claim 1 , further comprising:
printing, on a tail portion of the circuit board via a thick-film carbon deposition, resistors; and
electrically connecting the resistors to respective traces of at least one of the first traces or the second traces.
8. The method of claim 1 , wherein the forming of the first traces between the second traces comprises forming the first traces between the second traces based on a 1.0 mm pitch between the first traces and the second traces.
9. The method of claim 1 , wherein the forming of the first traces between the second traces comprises forming the first traces between the second traces based on a 1.25 mm pitch between the first traces and the second traces.
10. A two-layer printed circuit board (PCB), comprising:
an array of sensors that has been formed on a first side of the two-layer PCB; and
first traces alternately routed between second traces on a second side of the two-layer PCB in a singular direction, wherein the first traces are electrically coupled to respective rows of the array of sensors, and wherein the second traces are electrically coupled to respective columns of the array of sensors.
11. The two-layer PCB of claim 10 , wherein the sensors comprise force-based sensors.
12. The two-layer PCB of claim 10 , wherein the sensors comprise a variable impedance array (VIA) of sensors comprising variable impedance elements that interconnect with respective row and column cross points of the VIA of sensors.
13. The two-layer PCB of claim 10 , wherein the first traces are electrically coupled to the respective rows utilizing respective vias connecting the first traces to the respective rows.
14. The two-layer PCB of claim 10 , wherein the second traces are electrically coupled to the respective columns utilizing respective vias connecting the second traces to the respective columns.
15. The two-layer PCB of claim 10 , wherein resistors are connected between respective traces of the first traces.
16. The two-layer PCB of claim 10 , wherein resistors are connected between respective traces of the second traces.
17. The two-layer PCB of claim 10 , wherein surface mount resistors of a tail portion of the two-layer PCB are connected to respective traces of at least one of the first traces or the second traces.
18. The two-layer PCB of claim 10 , wherein a tail portion of the two-layer PCB comprises pins that are connected to respective traces of at least one of the first traces or the second traces.
19. The two-layer PCB of claim 10 , wherein the first side of the two-layer PCB comprises Kapton.
20. The two-layer PCB of claim 10 , wherein the first side of the two-layer PCB comprises FR4.