Low-latency digital signature processing with side-channel security
A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.
1. An apparatus comprising:
a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and
one or more accessory operation circuits coupled with the NTT/INTT coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit;
wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory, and wherein the computation by the one or more accessory operation circuits is performed without retrieving the results of the operations of the NTT/INTT coefficient multiplier circuit from the memory.
2. The apparatus of claim 1 , wherein the one or more accessory operation circuits are to perform the accessory operations in a same cycle as the operations of the NTT/INTT coefficient multiplier circuit.
3. The apparatus of claim 2 , wherein the performance of the one or more accessory operations overlaps at least in part with one or more other operations of the apparatus.
4. The apparatus of claim 1 , wherein the polynomial multiplication includes multiplying a private polynomial with a public polynomial.
5. The apparatus of claim 1 , wherein the polynomial multiplication is performed for digital signature processing.
6. The apparatus of claim 5 , wherein the digital signature processing is based on Crystals-Dilithium post-quantum digital signature technology.
7. The apparatus of claim 1 , wherein the one or more accessory operation circuits inherit one or more side-channel attack countermeasures from INTT circuitry of the NTT/INTT coefficient multiplier circuit.
8. The apparatus of claim 7 , wherein the one or more inherited side-channel attack countermeasures include shuffling of processing order.
9. A method comprising:
performing polynomial multiplication in an apparatus, the polynomial multiplication including Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and
performing one or more accessory operations in the apparatus, each of the one or more accessory operations including a computation based at least in part on a result of an operation of the NTT/INTT processing;
wherein the one or more accessory operations are to receive results of the NTT/INTT processing prior to the results being stored in a memory, and wherein the computation by the one or more accessory operations is performed without retrieving the results of the operations of the NTT/INTT processing from the memory.
10. The method of claim 9 , wherein the accessory operations are performed in a same cycle as the NTT/INTT processing.
11. The method of claim 10 , wherein performing of the one or more accessory operations overlaps at least in part with one or more other operations of the apparatus.
12. The method of claim 9 , wherein the polynomial multiplication includes multiplying a private polynomial with a public polynomial.
13. The method of claim 9 , wherein the polynomial multiplication is performed for digital signature processing.
14. The method of claim 13 , wherein the digital signature processing is based on Crystals-Dilithium post-quantum digital signature technology.
15. The method of claim 9 , wherein the one or more accessory operations inherit one or more side-channel attack countermeasures from the INTT processing.
16. The method of claim 15 , wherein the one or more inherited side-channel attack countermeasures include shuffling of processing order.
17. One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
performing polynomial multiplication in an apparatus, the polynomial multiplication including Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and
performing one or more accessory operations in the apparatus, each of the one or more accessory operations including a computation based at least in part on a result of an operation of the NTT/INTT processing;
wherein the one or more accessory operations are to receive results of the NTT/INTT processing prior to the results being stored in a memory, and wherein the computation by the one or more accessory operations is performed without retrieving the results of the operations of the NTT/INTT processing from the memory.
18. The storage mediums of claim 17 , wherein the accessory operations are performed in a same cycle as the NTT/INTT processing.
19. The storage mediums of claim 18 , wherein performing of the one or more accessory operations overlaps at least in part with one or more other operations of the apparatus.
20. The storage mediums of claim 17 , wherein the polynomial multiplication includes multiplying a private polynomial with a public polynomial.
21. The storage mediums of claim 17 , wherein the polynomial multiplication is performed for digital signature processing.