IP Library › Granted Patent US 12,635,230
Granted Patent B2
US 12,635,230 · App. 17/485,340 · Granted May 19, 2026

Transistor structures with reduced source/drain leakage through backside treatment of subfin semiconductor material

Inventors: Rishabh Mehandru (Portland, OR); Stephen Cea (Hillsboro, OR); Patrick Keys (Portland, OR); Aaron Lilak (Beaverton, OR); Cory Weber (Hillsboro, OR)
Assignee: Intel Corporation
H10D84/834H10D30/024H10D30/6211H10D84/013H10D84/0158H10D84/038H10P14/6349
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Quick Facts
Patent No.
US 12,635,230
App. No.
17/485,340
Granted
May 19, 2026
Kind
B2
Abstract

Integrated circuitry comprising transistor structures having a channel portion over a base portion of fin. The base portion of the fin is an insulative amorphous oxide, or a counter-doped crystalline material. Transistor structures, such as channel portions of a fin and source and drain materials may be first formed with epitaxial processes seeded by a front side of a crystalline substrate. Following front side processing, a backside of the transistor structures may be exposed and the base portion of the fin modified from the crystalline substrate composition into the amorphous oxide or counter-doped crystalline material using backside processes and low temperatures that avoid degradation to the channel material while reducing transistor off-state leakage.

Claims (31)

1 . An integrated circuit (IC) structure, comprising:

one or more levels of metallization on a frontside of a transistor structure, wherein the transistor structure further comprises:

a channel portion of a fin;

a source material and a drain material at opposite ends of channel portion, wherein the source and drain materials are crystalline; and

a gate stack adjacent to the channel portion; and

a base portion of the fin on a backside of the transistor structure, wherein:

the gate stack is between, and in direct contact with, a center length of the base portion and the channel portion of the fin;

a first end length of the base portion is in direct contact with the source material;

a second end length of the base portion is in direct contact with the drain material; and

the base portion is an amorphous material comprising oxygen, and Si or Ge and a metal impurity associated with a catalytic oxidation of the Si or Ge within the base portion; and

an isolation dielectric adjacent to a sidewall of the base portion.

2 . The IC structure of claim 1 , wherein the metal impurity is Al.

3 . The IC structure of claim 1 , wherein:

the source material and the drain material comprise Si and Ge;

the base portion comprises Si and is substantially free of Ge; and

the channel portion is under compressive strain associated with lattice mismatch between a lattice constant of monocrystalline Si and a lattice constant associated with the source and drain material.

4 . The IC structure of claim 1 , wherein the isolation dielectric has a composition distinct from that of the base portion of the fin.

5 . An integrated circuit (IC) structure, comprising:

one or more levels of metallization on a frontside of a transistor structure, wherein the transistor structure further comprises:

a channel portion of a fin;

a source material and a drain material at opposite ends of channel portion, wherein the source and drain materials are crystalline, and comprise Si, and a donor impurity; and

a gate stack adjacent to the channel portion; and

a base portion of the fin on a backside of the transistor structure, wherein:

the gate stack is between, and in direct contact with, a center length of the base portion and the channel portion of the fin;

a first end length of the base portion is in direct contact with the source material;

a second end length of the base portion is in direct contact with the drain material; and

the base portion comprises oxygen, Al, and Si or Ge; and

a dielectric material adjacent to a sidewall of the base portion.

6 . A computer system, comprising:

a power supply; and

an IC die coupled to the power supply, wherein the IC die comprises the IC structure of claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2021
From: MEHANDRU, RISHABH; CEA, STEPHEN; KEYS, PATRICK; LILAK, AARON; WEBER, CORY
To: INTEL CORPORATION
Reel/Frame 058110/0552 →
Continuity (1)
Related Publication 20230097948A1 · Mar 30, 2023
References Cited (9)
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