Memory pipeline control in a hierarchical memory system
In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.
1. An integrated circuit device comprising:
a processor core; and
a cache memory hierarchy coupled to the processor core that includes:
a cache memory; and
a cache memory controller circuit coupled to the cache memory that includes:
a memory pipeline associated with the cache memory;
a pipeline bypass path; and
a scheduler circuit coupled to the memory pipeline and the pipeline bypass path and configured to:
receive a write transaction;
determine whether the write transaction specifies a write to the cache memory;
when the write transaction does not specify a write to the cache memory, determine whether an intervening memory transaction inhibits use of the pipeline bypass path; and
provide the write transaction for a subsequent memory via either the memory pipeline or the pipeline bypass path based on whether the write transaction specifies a write to the cache memory and whether the intervening memory transaction inhibits use of the pipeline bypass path.
2. The integrated circuit device of claim 1 , wherein the scheduler circuit is configured to determine that the intervening memory transaction inhibits use of the pipeline bypass path based on the intervening memory transaction being associated with a snoop response.
3. The integrated circuit device of claim 1 , wherein:
the cache memory is a first cache memory;
the cache memory hierarchy includes a second cache memory arranged between the first cache memory and the processor core; and
the scheduler circuit is configured to determine that the intervening memory transaction inhibits use of the pipeline bypass path based on the intervening memory transaction being associated with memory synchronization of the second cache memory.
4. The integrated circuit device of claim 3 , wherein:
the second cache memory includes a victim cache; and
the memory synchronization of the second cache memory is associated with the victim cache.
5. The integrated circuit device of claim 3 , wherein:
the first cache memory is an L2 cache memory; and
the second cache memory is an L1 cache memory.
6. The integrated circuit device of claim 3 , wherein the scheduler circuit is configured to provide the write transaction for the subsequent memory via the memory pipeline associated with a priority that inhibits blocking and stalling of the write transaction based on the intervening memory transaction being associated with memory synchronization of the second cache memory.
7. The integrated circuit device of claim 1 , wherein the scheduler circuit is configured to determine whether the intervening memory transaction delays use of the pipeline bypass path.
8. The integrated circuit device of claim 7 , wherein:
the cache memory is a first cache memory;
the cache memory hierarchy includes a second cache memory arranged between the first cache memory and the processor core; and
the scheduler circuit is configured to determine that the intervening memory transaction delays use of the pipeline bypass path when the intervening memory transaction is associated with a write to the second cache memory.
9. The integrated circuit device of claim 8 , wherein:
the first cache memory is an L2 cache memory; and
the second cache memory is an L1 cache memory.
10. The integrated circuit device of claim 7 , wherein the scheduler circuit is configured to provide the write transaction for the subsequent memory via the pipeline bypass path after the intervening memory transaction completes with respect to the cache memory when the intervening memory transaction delays use of the pipeline bypass path.
11. The integrated circuit device of claim 1 , wherein the scheduler circuit is configured to determine that the write transaction does not specify a write to the cache memory based on a payload size of the write transaction.
12. The integrated circuit device of claim 1 , wherein the scheduler circuit is configured to determine that the write transaction does not specify a write to the cache memory based on a data type associated with the write transaction.
13. The integrated circuit device of claim 1 further comprising the subsequent memory, wherein:
the cache memory is an L2 cache memory; and
the subsequent memory is an L3 cache memory.
14. An integrated circuit device comprising:
a processor core;
an L1 cache controller coupled to the processor core;
an L1 cache memory coupled to the L1 cache controller;
an L2 cache controller coupled to the L1 cache controller;
an L2 cache memory coupled to the L2 cache controller;
wherein the L2 cache controller includes:
a memory pipeline associated with the L2 cache memory;
a pipeline bypass path; and
a scheduler circuit coupled to the memory pipeline and the pipeline bypass path and configured to:
receive a write transaction from the L1 cache memory;
determine whether the write transaction specifies a write to the L2 cache memory;
when the write transaction does not specify a write to the L2 cache memory, determine whether an intervening memory transaction inhibits servicing the write transaction using the pipeline bypass path; and
cause the write transaction to be provided to either the memory pipeline or the pipeline bypass path based on whether the write transaction specifies a write to the L2 cache memory and whether the intervening memory transaction inhibits servicing the write transaction using of the pipeline bypass path.
15. The integrated circuit device of claim 14 further comprising an L3 cache controller coupled to the L2 cache controller, wherein the scheduler circuit is further configured to cause the write transaction to be provided to the L3 cache controller via either the memory pipeline or the pipeline bypass path.
16. The integrated circuit device of claim 14 , wherein the scheduler circuit is configured to determine that the intervening memory transaction inhibits servicing the write transaction using the pipeline bypass path based on the intervening memory transaction being associated with memory synchronization of the L1 cache memory.
17. A method comprising:
receiving a memory transaction at a cache controller that includes a memory pipeline configured to write to a cache memory and includes a pipeline bypass path;
determining whether the memory transaction is associated with a write to the cache memory;
determining whether a preceding memory transaction inhibits servicing the memory transaction via the pipeline bypass path;
selecting a resource for servicing the memory transaction from among the memory pipeline and the pipeline bypass path based on whether the memory transaction is associated with a write to the cache memory and whether the preceding memory transaction inhibits servicing the memory transaction via the pipeline bypass path; and
servicing the memory transaction via the resource.
18. The method of claim 17 , wherein the selecting of the resource is such that the memory transaction is serviced via the memory pipeline when the preceding memory transaction is associated with a snoop response.
19. The method of claim 17 , wherein:
the cache memory is a first cache memory; and
the servicing of the memory transaction via the resource includes servicing the memory transaction via the memory pipeline and associated with a priority that inhibits blocking and stalling of the memory transaction based on the preceding memory transaction being associated with memory synchronization of a second cache memory.
20. The method of claim 17 further comprising determining whether the preceding memory transaction delays the servicing of the memory transaction via the pipeline bypass path, wherein the servicing of the memory transaction via the resource includes servicing the memory transaction via the pipeline bypass pass after the preceding memory transaction completes based on the preceding memory transaction delaying the servicing of the memory transaction via the pipeline bypass path.