Gallium nitride transistor
View Patent ↗A transistor device including a layer of AlGaN extending between a source and drain of the device; a GaN channel layer extending under the AlGaN layer; a gate stack including a layer of p-doped gallium nitride; and a layer of p-doped InGaN of at least 5 nm in thickness positioned between the AlGaN layer and the p-doped gallium nitride layer, the InGaN layer having a length greater than a length of the gate stack.
1. A transistor device comprising:
a layer of aluminum gallium nitride (AlGaN) extending between a source and a drain of the device;
a gallium nitride (GaN) channel layer extending under the layer of AlGaN;
a gate stack comprising a layer of p-doped GaN; and
a layer of p-doped indium gallium nitride (InGaN) of at least 5 nm in thickness positioned between the layer of AlGaN and the layer of p-doped GaN, the layer of p-doped InGaN having a length greater than a length of the gate stack and of the layer of p-doped GaN,
wherein a drain-side edge of the layer of p-doped InGaN is separated from the drain and/or a source-side edge of the layer of p-doped InGaN is separated from the source.
2. The transistor device of claim 1 , wherein the length of the layer of p-doped InGaN is of at least 6 μm.
3. The transistor device of claim 1 , wherein the layer of p-doped InGaN has an Mg doping concentration of at least 5×10 18 cm −3 .
4. The transistor device of claim 3 , wherein the layer of p-doped InGaN has an Mg doping concentration of less than 1×10 19 cm −3 .
5. The transistor device of claim 1 , wherein the layer of p-doped InGaN has an In mole faction of at least 0.05.
6. The transistor device of claim 1 , wherein the layer of p-doped InGaN extends beyond a drain-side edge of the gate stack by at least 2.0 μm, the layer of p-doped InGaN being aligned on a side of the source with a source edge of the gate stack.
7. The transistor device of claim 1 , wherein the drain-side edge of the layer of p-doped InGaN is separated from the drain by a spacing of at least 4.0 μm.
8. The transistor device of claim 1 , wherein the gate stack comprises a gate metal of Ni, W, or TiN.
9. The transistor device of claim 1 , wherein the layer of p-doped InGaN has a thickness of 7.5 nm or less.
10. The transistor device of claim 1 , comprising a source field plate extending from the source over the gate stack.
11. An integrated circuit comprising at least one transistor device according to claim 1 .
12. The transistor device of claim 1 , wherein the layer of p-doped InGaN has an Mg doping concentration of at least 7.5×10 18 cm −3 .
13. The transistor device of claim 1 , wherein the layer of p-doped InGaN has an In mole faction of between 0.10 and 0.20.