Memory device including phase change memory cell and operation method thereof
A memory device includes a phase change memory (PCM) cell connected between a bit line and a word line. An X-decoder provides a word line voltage to the word line during a reset operation, and a Y-decoder provides a bit line voltage to the bit line during the reset operation. A voltage bias circuit generates the word line voltage and the bit line voltage based on a first bias during a first period of the reset operation, the word line voltage and the bit line voltage based on a second bias greater than the first bias during a second period of the reset operation, and the word line voltage and the bit line voltage based on a third bias smaller than the first and second biases during a third period of the reset operation.
1. A memory device comprising:
a first phase change memory cell connected between a first bit line and a first word line;
an X-decoder configured to provide a selection word line voltage to the first word line during a reset write operation for changing a state of the first phase change memory cell from a set state to a reset state;
a Y-decoder configured to provide a selection bit line voltage to the first bit line during the reset write operation; and
a voltage bias circuit configured to:
generate the selection word line voltage and the selection bit line voltage based on a first voltage bias during a first period of the reset write operation,
generate the selection word line voltage and the selection bit line voltage based on a second voltage bias greater than the first voltage bias during a second period of the reset write operation, and
generate the selection word line voltage and the selection bit line voltage based on a third voltage bias smaller than the first voltage bias and the second voltage bias during a third period of the reset write operation.
2. The memory device of claim 1 , further comprising a current bias circuit configured to:
provide a first current bias to the first bit line during the first period of the reset write operation;
provide a second current bias to the first bit line during the second period of the reset write operation; and
provide a third current bias to the first bit line during the third period of the reset write operation.
3. The memory device of claim 2 , wherein:
the current bias circuit includes a plurality of switches and a plurality of capacitors, and
each of the plurality of switches and each of the plurality of capacitors are connected between an output node, from which the first to third current biases are respectively output in the first to third periods, and a specific voltage.
4. The memory device of claim 3 , further comprising a control logic circuit configured to control the plurality of switches.
5. The memory device of claim 2 , wherein:
the first current bias corresponds to a magnitude of a set write current,
the second current bias corresponds to a magnitude of a reset write current, and
the third current bias is equal to or smaller than a magnitude of a hold current, which is a minimum current for maintaining a turn-on state of the first phase change memory cell.
6. The memory device of claim 1 , wherein the first phase change memory cell includes:
an ovonic threshold switch (OTS) connected with the first bit line; and
a phase change material (GST) connected between the ovonic threshold switch and the first word line.
7. The memory device of claim 1 , wherein the first phase change memory cell includes:
an ovonic threshold switch (OTS) connected with the first word line; and
a phase change material (GST) connected between the ovonic threshold switch and the first bit line.
8. The memory device of claim 1 , wherein the first bit line extends in a first direction and the first word line extends in a second direction perpendicular to the first direction.
9. The memory device of claim 8 , further comprising a second phase change memory cell stacked above the first phase change memory cell in a direction perpendicular to a plane defined by the first direction and the second direction and connected with the first bit line and a second word line extending in the second direction.
10. The memory device of claim 1 , further comprising a compensation circuit configured to apply an offset, which is determined based on a temperature of the memory device or a physical location of the first phase change memory cell, to each of the first to third voltage biases.