Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.
1. A chip package comprising:
a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;
a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;
a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; and
a plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.
2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a semiconductor integrated-circuit (IC) chip of the chip package.
3. The chip package of claim 2 further comprising an interconnection scheme under and coupling to the semiconductor integrated-circuit (IC) chip and across an edge of the semiconductor integrated-circuit (IC) chip, wherein the interconnection scheme comprises a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer, an inter-metal layer between the first and second interconnection metal layers, wherein the second interconnection metal layer couples to the first interconnection metal layer through an opening in the inter-metal layer, a plurality of contact points at a bottom of the interconnection scheme, and a bottom layer at the bottom of the interconnection scheme, wherein a plurality of openings in the bottom layer are under the plurality of contact points respectively, wherein each of the plurality of metal bumps is on one of the plurality of contact points, wherein said each of the plurality of metal bumps comprises a tin-containing layer.
4. The chip package of claim 3 , wherein said each of the plurality of metal bumps comprises an adhesion layer on one of the plurality of contact points and a bottom surface of the bottom layer, and a copper layer under and on the adhesion layer, wherein the tin-containing layer is under the copper layer.
5. The chip package of claim 4 , wherein the adhesion layer comprises titanium.
6. The chip package of claim 3 , wherein the bottom layer comprises a polymer.
7. The chip package of claim 1 , wherein the non-volatile memory cell is a resistive-random-access-memory (RRAM) cell configured to store the resulting data of the look-up table (LUT) therein.
8. The chip package of claim 7 , wherein the resistive-random-access-memory (RRAM) cell comprises two electrodes and a resistive layer between the two electrodes.
9. The chip package of claim 1 , wherein the non-volatile memory cell is a magnetoresistive-random-access-memory (MRAM) cell configured to store the resulting data of the look-up table (LUT) therein.
10. The chip package of claim 9 , wherein the magnetoresistive-random-access-memory (MRAM) cell comprises an antiferromagnetic layer, a first magnetic layer, a second magnetic layer between the antiferromagnetic layer and first magnetic layer, and an oxide layer between the first and second magnetic layers.
11. A chip package comprising:
a non-volatile memory cell configured to store a code therein;
a sense amplifier configured to sense input data thereof associated with the code stored in the non-volatile memory cell to generate output data of the sense amplifier;
a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier;
an interconnection circuit comprising a switch circuit having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, and first and second interconnects coupling to the switch circuit, wherein the switch circuit is configured to control, in accordance with the second data of the switch circuit, coupling between the first and second interconnects; and
a plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.
12. The chip package of claim 11 , wherein the sense amplifier, static-random-access-memory (SRAM) cell and interconnection circuit are provided by a semiconductor integrated-circuit (IC) chip of the chip package.
13. The chip package of claim 12 further comprising an interconnection scheme under and coupling to the semiconductor integrated-circuit (IC) chip and across an edge of the semiconductor integrated-circuit (IC) chip, wherein the interconnection scheme comprises a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer, an inter-metal layer between the first and second interconnection metal layers, wherein the second interconnection metal layer couples to the first interconnection metal layer through an opening in the inter-metal layer, a plurality of contact points at a bottom of the interconnection scheme, and a bottom layer at the bottom of the interconnection scheme, wherein a plurality of openings in the bottom layer are under the plurality of contact points respectively, wherein each of the plurality of metal bumps is on one of the plurality of contact points, wherein said each of the plurality of metal bumps comprises a tin-containing layer.
14. The chip package of claim 13 , wherein said each of the plurality of metal bumps further comprises an adhesion layer on one of the plurality of contact points and a bottom surface of the bottom layer, and a copper layer under and on the adhesion layer, wherein the tin-containing layer is under the copper layer.
15. The chip package of claim 14 , wherein the adhesion layer comprises titanium.
16. The chip package of claim 13 , wherein the bottom layer comprises a polymer.
17. The chip package of claim 11 , wherein the non-volatile memory cell is a resistive-random-access-memory (RRAM) cell configured to store the code therein.
18. The chip package of claim 17 , wherein the resistive-random-access-memory (RRAM) cell comprises two electrodes and a resistive layer between the two electrodes.
19. The chip package of claim 11 , wherein the non-volatile memory cell is a magnetoresistive-random-access-memory (MRAM) cell configured to store the code therein.
20. The chip package of claim 19 , wherein the magnetoresistive-random-access-memory (MRAM) cell comprises an antiferromagnetic layer, a first magnetic layer, a second magnetic layer between the antiferromagnetic layer and first magnetic layer, and an oxide layer between the first and second magnetic layers.