IP Library › Granted Patent US 12,004,355
Granted Patent B2
US 12,004,355 · App. 17/498,023 · Granted Jun 4, 2024

Magnetic tunnel junction element and magnetoresistive memory device

Inventors: Yoshiaki Sonobe (Fujisawa, JP); Hideto Yanagihara (Tsukuba, JP)
Assignee: Samsung Electronics Co., Ltd.
H10B61/00H01F10/3254H01F10/3268H01F10/3286H10N50/10H10N50/80H01F10/329H10N50/85
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Quick Facts
Patent No.
US 12,004,355
App. No.
17/498,023
Granted
Jun 4, 2024
Kind
B2
Abstract

Provided is a magnetic tunnel junction element and a magnetoresistive memory device. The magnetic tunnel junction element includes a fixed layer maintaining a magnetization direction, an insulating layer, a free layer having a variable magnetization direction, and an antiferromagnetic oxide layer. The fixed layer, the free layer, and the antiferromagnetic oxide layer may be sequentially stacked. The free layer and the antiferromagnetic oxide layer may be in direct contact with each other.

Claims (57)

1. A magnetic tunnel junction element comprising:

a fixed layer maintaining a magnetization direction;

an insulating layer;

a free layer having a variable magnetization direction; and

an antiferromagnetic oxide layer in direct contact with the free layer, wherein

the fixed layer, the free layer, the insulating layer, and the antiferromagnetic oxide layer are sequentially stacked,

a thickness of the antiferromagnetic oxide layer is greater than or equal to about 0.5 nm and less than or equal to about 2 nm, and

wherein an electrical resistance of the antiferromagnetic oxide layer is less than an electrical resistance of the insulating layer.

2. The magnetic tunnel junction element of claim 1 ,

wherein

a magnetic anisotropy of the free layer is in a direction perpendicular to a stack surface, and

the direction perpendicular to the stack surface extends from a lower surface to an upper surface of a stack structure including the fixed layer, the free layer, the insulating layer, and the antiferromagnetic oxide layer.

3. The magnetic tunnel junction element of claim 2 , wherein

a direction of a bias magnetic field generated from the antiferromagnetic oxide layer is parallel to the stack surface, and

a direction parallel to the stack surface is parallel to the lower surface of a stack structure.

4. The magnetic tunnel junction element of claim 1 , wherein

a thickness of the free layer is greater than or equal to about 0.6 nm and less than or equal to about 1 nm,

a magnetic anisotropy of the free layer is in a direction perpendicular to a stack surface, and

the direction perpendicular to the stack surface extends from a lower surface to an upper surface of a stack structure including the fixed layer, the free layer, the insulating layer, and the antiferromagnetic oxide layer.

5. The magnetic tunnel junction element of claim 1 , the antiferromagnetic oxide layer includes CoO, a mixture of NiO and CoO, NiO and VO, or a combination of MnO, CoO, and CuO.

6. The magnetic tunnel junction element of claim 1 , wherein

a thickness of the free layer is about 0.6 nm to about 1 nm.

7. The magnetic tunnel junction element of claim 1 , wherein

the fixed layer includes a first fixed layer and a second fixed layer on the first fixed layer,

the first fixed layer includes CoFeB as a main component,

the second fixed layer includes a Co/Pt multilayer film,

the second fixed layer is on the first fixed layer, and

the second fixed layer is between the first fixed layer and the insulating layer.

8. The magnetic tunnel junction element of claim 7 , wherein the insulating layer includes one of MgO, CaO, SrO, ViO, VO, NbO, or MgAl 2 O 4 .

9. The magnetic tunnel junction element of claim 7 , wherein

the first fixed layer further includes a Co-based full-Heusler alloy,

the free layer includes a Co-based full-Heusler alloy, a MnGaGe-based material, or a FeNi-based material.

10. A magnetoresistive memory device comprising:

a magnetic tunnel junction element including a fixed layer maintaining a magnetization direction, an insulating layer, a free layer having a variable magnetization direction, and an antiferromagnetic oxide layer in direct contact with the free layer, wherein the fixed layer, the insulating layer, the free layer, and the antiferromagnetic oxide layer are sequentially stacked, a thickness of the antiferromagnetic oxide layer is greater than or equal to about 0.5 nm and less than or equal to about 2 nm; and

an electrode configured to apply a voltage to the magnetic tunnel junction element, wherein

an electrical resistance of the antiferromagnetic oxide layer is less than an electrical resistance of the insulating layer.

11. The magnetoresistive memory device of claim 10 , wherein

a magnetic anisotropy of the free layer is in a direction perpendicular to a stack surface, and

the direction perpendicular to the stack surface extends from a lower surface to an upper surface of a stack structure including the fixed layer, the free layer, the insulating layer, and the antiferromagnetic oxide layer.

12. The magnetoresistive memory device of claim 11 , wherein

a direction of a bias magnetic field generated from the antiferromagnetic oxide layer is parallel to the stack surface, and

a direction parallel to the stack surface is parallel to the lower surface of the stack structure.

13. The magnetoresistive memory device of claim 10 , wherein a thickness of the free layer is greater than or equal to about 0.6 nm and less than or equal to about 1 nm,

a magnetic anisotropy of the free layer is in a direction perpendicular to a stack surface, and

the direction perpendicular to the stack surface extends from a lower surface to an upper surface of a stack structure including the fixed layer, the free layer, the insulating layer, and the antiferromagnetic oxide layer.

14. The magnetoresistive memory device of claim 13 , wherein the antiferromagnetic oxide layer includes CoO, a mixture of NiO and CoO, NiO and VO, or a combination of MnO, CoO, and CuO.

15. The magnetoresistive memory device of claim 10 , wherein a thickness of the free layer is about 0.6 nm to about 1 nm.

16. The magnetoresistive memory device of claim 10 , wherein

the fixed layer includes a first fixed layer and a second fixed layer on the first fixed layer,

the first fixed layer includes CoFeB as a main component,

the second fixed layer includes a Co/Pt multilayer film,

the second fixed layer is on the first fixed layer, and

the second fixed layer is between the first fixed layer and the insulating layer.

17. The magnetoresistive memory device of claim 10 , wherein the insulating layer includes one of MgO, CaO, SrO, ViO, VO, NbO, or MgAl 2 O 4 .

18. The magnetoresistive memory device of claim 10 , wherein

the fixed layer further includes a Co-based full-Heusler alloy,

the free layer includes a Co-based full-Heusler alloy, a MnGaGe-based material, or a FeNi-based material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2021
From: SONOBE, YOSHIAKI; YANAGIHARA, HIDETO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 057775/0718 →
Priority Claims (2)
JP 2020-178331 · Oct 23, 2020 · national
KR 10-2020-0173582 · Dec 11, 2020 · national
Continuity (1)
Related Publication 20220130901A1 · Apr 28, 2022