IP Library Granted Patent US 11,843,008
Granted Patent B2
US 11,843,008 · App. 17/498,286 · Granted Dec 12, 2023

SPAD pixel

Inventors: Francois Guyader (Montbonnot, GB); Sara Pellegrini (Edinburgh, GB); Bruce Rae (Edinburgh, GB)
Assignees: STMicroelectronics (Crolles 2) SAS; STMicroelectronics (Research & Development) Limited
H01L27/1461G01J1/44H01L27/14634H01L31/107H04N25/70G01J2001/4466
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Quick Facts
Patent No.
US 11,843,008
App. No.
17/498,286
Granted
Dec 12, 2023
Kind
B2
Abstract

An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

Claims (11)

1. A method of manufacturing an electronic device which includes a stack of a first level comprising a SPAD, a second level comprising a quench circuit for said SPAD, and a third level comprising a circuit for processing data generated by said SPAD, the method comprising:

a) forming said first level consisting of a first semiconductor layer including a SPAD and a first insulating layer;

b) forming a stack of layers of the second level comprising a second semiconductor layer, a first interconnection layer including first pads and a second insulating layer;

c) bonding by molecular bonding the second insulating layer of said stack of layers to the first insulating layer of the first level;

d) forming said quench circuit in the second semiconductor layer;

e) forming a stack of layers of the third level comprising a third semiconductor layer and a second interconnection layer including second pads; and

f) bonding by hybrid bonding the first and second interconnection layers and first and second pads.

2. The method according to claim 1 , wherein the second semiconductor layer is etched, after step c), to form a plurality of distinct regions.

3. The method according to claim 1 , wherein the first level comprises no electronic component other than the SPAD.

4. The method of claim 1 , wherein the first level comprises a single SPAD.

5. The method of claim 1 , wherein the second level only comprises said quench circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2021
From: GUYADER, FRANCOIS
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 057753/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2021
From: PELLEGRINI, SARA; RAE, BRUCE
To: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
Reel/Frame 057753/0510 →
Priority Claims (1)
FR 2010400 · Oct 12, 2020 · national
Continuity (1)
Related Publication 20220115419A1 · Apr 14, 2022