Neural network accelerator writable memory

1. An integrated circuit comprising:

an accumulation memory;

a plurality of convolution modules comprising circuitry configured to perform mathematical operations on input values;

a plurality of adder modules comprising circuitry configured to sum values output from the plurality of convolution modules; and

a plurality of convolution output interconnects connecting the plurality of convolution modules, the plurality of adder modules, and the accumulation memory;

wherein the accumulation memory is an accumulation memory allocation of a writable memory block having a reconfigurable bank width; and

wherein each bank of the accumulation memory allocation is a virtual combination of consecutive banks of the writable memory block.

2. The integrated circuit according to claim 1 , further comprising:

a convolution output interconnect control module configured to open and close convolution output interconnects according to a convolution output connection scheme;

wherein each convolution module has a direct connection to each adder module and the accumulation memory, and each adder module has a direct connection to the accumulation memory; and

wherein, in accordance with the convolution output scheme, each convolution module has no more than one open direct connection through the plurality of convolution output interconnects to the accumulation memory or one of the plurality of adder modules.

3. The integrated circuit according to claim 2 , wherein the convolution output connection scheme includes more than one convolution module among the plurality of convolution modules having an open direct connection to a common adder module among the plurality of adder modules.

4. The integrated circuit according to claim 1 , further comprising:

one or more sequencer modules configured to synchronize the operations of the plurality of convolution modules.

5. The integrated circuit according to claim 1 , further comprising:

an input data memory, the input data memory allocation storing the input values;

wherein the input data memory is an input data memory allocation of the writable memory block; and

wherein each bank of the input data memory allocation is a virtual combination of consecutive banks of the writable memory block.

6. The integrated circuit according to claim 5 , further comprising

a line buffer in communication with the input data memory and the plurality of convolution modules, the line buffer including a plurality of indices; and

a plurality of convolution input interconnects connecting the plurality of indices, the plurality of convolution modules, and the input data memory, such that each convolution module has a direct connection to each index and the input data memory; and

a convolution input interconnect control module configured to open and close convolution input interconnects according to a convolution input connection scheme whereby each convolution module has no more than one open direct connection through the plurality of convolution input interconnects to the input data memory or one of the plurality of indices.

7. The integrated circuit according to claim 1 , further comprising:

an input data memory, the input data memory allocation storing the input values;

wherein the input data memory is an input data memory allocation of the writable memory block; and

wherein each bank of the input data memory allocation is a bank of the writable memory block.

8. The integrated circuit according to claim 7 , wherein

the writable memory block has a bank width of 8 bits;

each bank of the input data memory allocation is a 8-bit bank of the writable memory block; and

each bank of the accumulation memory allocation is a 32-bit virtual combination of four consecutive 8-bit banks of the writable memory block.

9. The integrated circuit according to claim 1 , wherein

each bank of the accumulation memory allocation is a virtual combination of a first number of consecutive banks of the writable memory block.

10. The integrated circuit according to claim 9 , further comprising:

a processor configured to

receive an instruction for reconfiguring the writable memory block, and

reconfigure the accumulation memory allocation according to the instruction so that each bank of the accumulation memory allocation is a virtual combination of a second number of consecutive banks of the writable memory block.