IP Library › Granted Patent US 11,527,571
Granted Patent B2
US 11,527,571 · App. 17/498,687 · Granted Dec 13, 2022

Light emitting device with small footprint

Inventor: Scott Brad Herner (Portland, OR)
Assignee: Black Peak LLC
H01L27/15H01L25/167
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Quick Facts
Patent No.
US 11,527,571
App. No.
17/498,687
Granted
Dec 13, 2022
Kind
B2
Abstract

This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.

Claims (21)

1. A method for forming a light emitting device, the method comprising:

providing a transistor substrate having a top surface and a bottom surface, the top surface comprising a plurality of conductive regions;

forming two transistors in the top surface of the transistor substrate and a capacitor, wherein the longest dimension of the capacitor is substantially orthogonal to the top surface of the transistor substrate and wherein the capacitor is in operative communication with the two transistors;

providing an LED substrate;

forming an LED on the LED substrate, the LED having a largest area and wherein the LED comprises gallium nitride, indium gallium nitride, indium arsenide, aluminum gallium arsenide, gallium arsenide, gallium phosphide, gallium arsenide phosphide, aluminum indium gallium phosphide, gallium arsenide nitride, aluminum indium arsenide, aluminum antimonide, indium phosphide, indium antimonide, or indium gallium arsenide phosphide, and combinations thereof;

forming a reflector layer;

bonding the two transistors, capacitor, and transistor substrate to the LED, wherein after bonding, the reflector layer is disposed between the LED and the transistor substrate, the LED is in operative communication with at least one of the two transistors, and the LED overlies the two transistors and capacitor;

removing a portion of the transistor substrate; and

forming a plurality of through substrate interconnects, wherein each through substrate interconnect of the plurality extends through the transistor substrate from the conductive region of the plurality of conductive regions to the bottom surface of the transistor substrate.

2. The method of claim 1 , wherein the capacitor is a stack capacitor disposed between either the first transistor or the second transistor and the LED.

3. The method of claim 1 , wherein the capacitor is a trench capacitor wherein at least a portion of the trench capacitor is disposed between the top surface and the bottom surface of the transistor substrate.

4. The method of claim 1 , wherein the transistor substrate comprises single crystal silicon.

5. The method of claim 1 , wherein the transistor substrate comprises an etch-stop layer.

6. The method of claim 1 , wherein after the step of removing a portion of the transistor substrate step, the transistor substrate has a thickness less than 20 microns.

7. The method of claim 1 , wherein the reflector layer comprises a distributed Bragg reflector.

8. The method of claim 1 , further comprising providing a backboard, wherein the backboard comprises an interposer, wherein the interposer comprises a plurality of backboard interconnects.

9. The method of claim 8 , further comprising bonding each through substrate interconnect of the plurality of through substrate interconnects to a backboard interconnect of the plurality of backboard interconnects.

10. The method of claim 9 , further comprising removing the LED substrate.

11. The method of claim 1 , further comprising providing a wavelength-converting layer, wherein the wavelength-converting layer overlies the LED.

12. The method of claim 1 , wherein the largest area of the LED is 2,500 square microns or less.

13. The method of claim 1 , wherein the largest area of the LED is 100 square microns or less.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2026
From: HERNER, SCOTT BRAD
To: BLACK PEAK LLC
Reel/Frame 074168/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2026
From: BLACK PEAK LLC
To: ADEIA SEMICONDUCTOR INC.
Reel/Frame 074170/0919 →
Continuity (1)
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