Mitigating edge layer effect in partially written blocks
A storage device includes 3D NAND including layers of multi-level cells. When a shutdown command is received, whether a block is partially written is evaluated. If so, dummy lines are written after the last written wordline of the block. Partially written blocks may be those having a fill percentage less than a threshold. The threshold may be a function of the PEC count of the block. If a maximum retention time is exceeded by data stored in a partially written block, dummy lines may also be written to the block.
1. A storage system comprising:
a NAND storage device comprising a plurality of blocks of storage; and
a controller coupled to the NAND storage device and programmed to:
(a) identify one or more partially written blocks of the plurality of blocks of storage for which a written percentage of each block of the one or more partially written blocks is below a threshold percentage for each block of the one or more partially written blocks, the threshold percentage being a function of a number of program and erase cycles of each block of the one or more partially written blocks and being selected such that failed bit counts remain correctable according to error correction implemented by the NAND storage device; and
(b) in response to the written percentage of each block of the one or more partially written blocks being below threshold, write one or more lines of dummy data to a layer following a last-written line of each block.
2. The storage system of claim 1 , wherein the controller is further programmed to perform (a) by determining that the one or more partially written blocks are not single-level cells (SLC).
3. The storage system of claim 1 , wherein the controller is further programmed to perform (a) by determining that a written percentage of each of the one or more partially written blocks is not equal to a predefined value.
4. The storage system of claim 1 , wherein the controller is further programmed to perform (a) by determining that there has not been a previous writing of dummy data to the one or more partially written blocks.
5. The storage system of claim 1 , wherein a number of the one or more lines of dummy data is equal to a number of wordlines in each layer of the NAND storage device.
6. The storage system of claim 5 , wherein the one or more lines of dummy data include at least four lines.
7. The storage system of claim 1 , wherein the NAND storage device is a three-dimensional NAND storage device.
8. The storage system of claim 1 , wherein the controller is programmed to perform (a) and (b) in response to receiving a shut down command.
9. The storage system of claim 1 , wherein the controller is programmed to perform (a) and (b) in response to determining that a maximum permitted retention time has elapsed for data written to the one or more partially written blocks.
10. A storage system comprising:
a NAND storage device comprising a plurality of blocks of storage; and
a controller coupled to the NAND storage device and programmed to:
evaluate frequency of writing and write amplification of the NAND storage device;
determining an expected retention time based on the frequency of writing and the write amplification of the NAND storage device; and
if the expected retention time is greater than a maximum allowed retention time:
track retention time of each block of the plurality of blocks of storage; and
write dummy data to each block of the plurality of blocks having a retention time exceeding the maximum allowed retention time and that is determined to be partially written;
wherein the controller is further programmed to determine whether each block of the plurality of blocks is partially written by determining that data written to each block is below a threshold percentage of a storage capacity of each block;
wherein the threshold percentage is a function of a number of program and erase cycles of each block and is selected such that failed bit counts remain correctable according to error correction implemented by the NAND storage device.
11. The storage system of claim 10 , wherein the expected retention time is a function of an amount of data written to the NAND storage device in a time period and write amplification of the NAND storage device.
12. The storage system of claim 10 , wherein the controller is programmed to reset the retention time of each block following writing the dummy data thereto.
13. The storage system of claim 10 , wherein the dummy data include at least four lines.
14. The storage system of claim 10 , wherein the NAND storage device is a three-dimensional NAND storage device.