Stacked transistor device
Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.
1. A method of forming a logic device, the method comprising:
forming an opening in a stack of pre-transistor layers to expose a surface of a substrate, the surface defining a horizontal plane with the stack of pre-transistor layers, each pre-transistor layer comprising a first film, a dummy gate, and a second film, each pre-transistor layer separated from adjacent layers by a pre-isolation layer, the first film and second film etch selective relative to the dummy gate and pre-isolation layer, and the dummy gate etch selective to the pre-isolation layer;
forming an epitaxial channel in the opening from the substrate surface to a top of the stack of pre-transistor layers;
forming an isolation trench in the stack of pre-transistor layers spaced from the epitaxial channel to expose the surface of the substrate;
replacing the pre-isolation layer with an isolation layer;
replacing the dummy gate with a high-k/metal gate; and
replacing the first film and the second film with a source/drain material.
2. The method of claim 1 , wherein each pre-transistor layer has a first end and a second end defining a length and the method further comprises forming a stepped region at the second end of each pre-transistor layer so that the length of each pre-transistor decreases with increasing distance from the horizontal plane of the substrate surface.
3. The method of claim 1 , wherein replacing the pre-isolation layer comprises selectively etching the pre-isolation layer to a depth extending to at least a surface of the epitaxial channel to form a gap, depositing the isolation layer in the gap and removing overburden from a surface of the stack.
4. A method of forming a semiconductor device, the method comprising:
forming an epitaxial channel orthogonally to a horizontal plane of a substrate surface, the epitaxial channel having a height extending above the substrate surface and a length extending along a first direction of the horizontal plane, the epitaxial channel having a first side and a second side; and
forming a stack of horizontal transistors on the substrate surface in contact with the first side or the second side of the epitaxial channel, the stack of horizontal transistors comprising a first horizontal transistor having a first length and a first step, a second horizontal transistor having a second length and a second step, and a third horizontal transistor having a third length and a third step, each of the horizontal transistors separated from adjacent layers by a horizontal isolation layer, each of the horizontal transistors comprising the horizontal isolation layer, a source region, a gate, and a drain region.
5. The method of claim 4 , wherein the epitaxial channel comprises one or more of silicon, indium phosphate, germanium, silicon germanium, and gallium arsenide.
6. The method of claim 4 , wherein the epitaxial channel is doped with a dopant selected from one or more of boron (B), arsenic (As), phosphorous (P), antimony (Sb), aluminum (Al), gallium (Ga), selenium (Se), tellurium (Te), magnesium (Mg), zinc (Zn), cadmium (Cd), silicon (Si), and germanium (Ge).
7. The method of claim 4 , further comprising forming a stair-case arrangement of the stack of horizontal transistors.
8. The method of claim 7 , further comprising covering the stair-case arrangement with a dielectric material.
9. The method of claim 8 , further comprising depositing an etch stop layer on the dielectric material.
10. The method of claim 9 , further comprising depositing a low-k dielectric fill material on the etch stop layer.
11. The method of claim 10 , further comprising forming a contact hole through the stair-case arrangement to connect the source region, the drain region, and the gate region for each of the horizontal transistors.
12. The method of claim 11 , further comprising filling the contact hole with a contact material.
13. The method of claim 12 , wherein the contact material comprises one or more of tungsten, cobalt, and ruthenium.
14. The method of claim 4 , wherein the horizontal isolation layer comprises a thermal oxide film.