Semiconductor structure and method for manufacturing the same
A semiconductor structure is provided. The semiconductor structure includes a substrate and a bottom dielectric layer continuously disposed on the substrate. The semiconductor structure further includes a plurality of stacks disposed on the bottom dielectric layer. Each of the stacks includes gate electrodes and semiconductor layers disposed alternately. The semiconductor structure further includes a plurality of source/drain structures disposed on the bottom dielectric layer and between the stacks. The semiconductor structure further includes a plurality of conductors landed on highest gate electrodes of the stacks.
1. A semiconductor structure, comprising:
a substrate;
a bottom dielectric layer continuously disposed on the substrate;
a plurality of stacks disposed on the bottom dielectric layer, each of the stacks comprising gate electrodes and semiconductor layers disposed alternately;
a plurality of source/drain structures disposed on the bottom dielectric layer and between the stacks; and
a plurality of conductors landed on highest gate electrodes of the stacks;
wherein an extending direction of the conductors is perpendicular to a direction directing from one of the source/drain structures disposed at a side of one of the stacks to corresponding one of the source/drain structures disposed at another side of the one of the stacks opposite to said side, wherein the bottom dielectric layer has thicker portions between the stacks along the extending direction of the conductors, and wherein the bottom dielectric layer has a continuous co-planar top surface.
2. The semiconductor structure according to claim 1 , wherein each of the stacks further comprising inner spacers disposed on sidewalls of the gate electrodes.
3. The semiconductor structure according to claim 1 , wherein the gate electrodes comprise a high k material and a metal gate material.
4. The semiconductor structure according to claim 1 , wherein the conductors comprise same materials as the gate electrodes.
5. The semiconductor structure according to claim 1 , wherein a horizontal size of the conductors is smaller a horizontal size of the gate electrodes.
6. The semiconductor structure according to claim 1 , further comprising:
outer spacers disposed on sidewalls of the conductors.
7. The semiconductor structure according to claim 1 , wherein each of the conductors electrically connects two or more of the stacks in the extending direction of the conductors, and a number of the source/drain structures in each row along the extending direction of the conductors corresponds to a number of the stacks electrically connected by one conductor.
8. The semiconductor structure according to claim 1 , wherein the bottom dielectric layer has a thickness of 5 nm to 100 nm.
9. The semiconductor structure according to claim 1 , wherein the stacks has a width of 2 nm to 200 nm.
10. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a bottom dielectric layer continuous on the substrate;
forming a plurality of stacks on the bottom dielectric layer, each of the stacks comprising gate electrodes and semiconductor layers disposed alternately;
forming a plurality of source/drain structures on the bottom dielectric layer and between the stacks; and
forming a plurality of conductors on highest gate electrodes of the stacks;
wherein an extending direction of the conductors is perpendicular to a direction directing from one of the source/drain structures disposed at a side of one of the stacks to corresponding one of the source/drain structures disposed at another side of the one of the stacks opposite to said side, wherein the bottom dielectric layer has thicker portions between the stacks along the extending direction of the conductors, and wherein the bottom dielectric layer has a continuous co-planar top surface.
11. The method according to claim 10 , comprising:
forming a plurality of preliminary stacks on the substrate, the preliminary stacks separated by a plurality of trenches, each of the preliminary stacks comprising sacrificial layers and semiconductor layers disposed alternately;
removing lowest sacrificial layers and lowest semiconductor layers of the preliminary stacks;
providing a bottom dielectric material which is provided to the trenches and further fills into spaces caused by removing the lowest sacrificial layers and the lowest semiconductor layers, so as to form the bottom dielectric layer;
dividing each of the preliminary stacks;
forming the source/drain structures on the bottom dielectric layer at spaces caused by dividing each of the preliminary stacks; and
replacing the remaining sacrificial layers of the preliminary stacks with gate electrodes, so as to form the stacks on the bottom dielectric layer.
12. The method according to claim 11 , wherein the lowest sacrificial layers of the preliminary stacks are disposed on the substrate, and the lowest semiconductor layers of the preliminary stacks are disposed on the lowest sacrificial layers, and wherein removing the lowest sacrificial layers and the lowest semiconductor layers of the preliminary stacks comprises:
forming barriers into the trenches, wherein the barriers have top surfaces aligned with top surfaces of the lowest sacrificial layers;
forming disposable spacers on sidewalls of the preliminary stacks, the disposable spacers stopping on the top surfaces of the barriers;
removing portions of the barriers covering the lowest sacrificial layers;
conducting a first selective etching process to remove the lowest sacrificial layers; and
conducting a second selective etching process to remove the lowest semiconductor layers.
13. The method according to claim 11 , after forming the bottom dielectric layer and before forming the source/drain structures, the method comprising:
providing a dummy gate material which fills into the trenches and covers the preliminary stacks;
providing a hard mask material onto the dummy gate material;
patterning the hard mask material and the dummy gate material, so as to form a plurality of dummy gates across the preliminary stacks with hard masks thereon;
forming outer spacers on sidewalls of the dummy gates with the hard masks thereon; and
removing portions of the preliminary stacks and portions of the dummy gate material using the hard masks and the outer spacers, so as to dividing each of the preliminary stacks.
14. The method according to claim 13 , further comprising:
conducting a pull back process to the sacrificial layers; and
forming inner spacers in spaces caused by the pull back process.
15. The method according to claim 13 , wherein in forming the source/drain structures, a number of the source/drain structures in each row along an extending direction of the dummy gates corresponds to a number of the preliminary stacks connected by one dummy gate, and the number of the source/drain structures in each row is two or more.
16. The method according to claim 13 , after forming the source/drain structures, the method comprising:
filling a dielectric material;
removing the hard masks, the dummy gates, and the remaining sacrificial layers of the preliminary stacks; and
forming the gate electrodes in spaces caused by removing the remaining sacrificial layers of the preliminary stacks; and
forming the conductors in spaces caused by removing the hard masks and the dummy gates.
17. The method according to claim 16 , wherein the gate electrodes and the conductors comprise same materials, and forming the gate electrodes and forming the conductors are finished at a common process.
18. The method according to claim 17 , the common process comprises:
forming a conformal layer of a high k material; and
filling a metal gate material.
19. The method according to claim 11 , wherein a horizontal size of the conductors as formed is smaller a horizontal size of the gate electrodes as formed.
20. The method according to claim 11 , wherein the bottom dielectric layer has a thickness of 5 nm to 100 nm, and the stacks has a width of 2 nm to 200 nm.