Compound semiconductor device
View Patent ↗Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate.
1. A compound semiconductor device comprising:
a first semiconductor layer having a fin extending in a first direction on a substrate;
an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer;
a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode;
a dielectric layer disposed between a top surface of the fin and the upper gate electrode; and
a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate;
wherein the upper gate electrode has a lower end disposed closer to the bottom surface of the first semiconductor layer than the top surface of the fin.
2. The compound semiconductor device of claim 1 , wherein the second semiconductor layer extends along the sidewall of the fin in the first direction.
3. The compound semiconductor device of claim 1 , wherein a width in the second direction of the second semiconductor layer is less than a height of the second semiconductor layer.
4. The compound semiconductor device of claim 1 , wherein the second semiconductor layer has a top surface disposed at a same vertical level as a top surface of the fin.
5. The compound semiconductor device of claim 1 , wherein the second semiconductor layer has a bandgap different from a bandgap of the first semiconductor layer.
6. The compound semiconductor device of claim 1 , wherein the dielectric layer covers a top surface of the second semiconductor layer.
7. The compound semiconductor device of claim 1 , further comprising source and drain contacts spaced apart from each other in the first direction and connected to the first semiconductor layer,
wherein the upper gate electrode is disposed between the source and drain contacts.
8. The compound semiconductor device of claim 1 , wherein the lower gate structure extends in the second direction.
9. The compound semiconductor device of claim 1 , wherein the lower gate structure vertically overlaps the upper gate electrode.
10. A compound semiconductor device comprising:
a first semiconductor layer having a fin extending in a first direction on a substrate;
an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer;
a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode;
a dielectric layer disposed between a top surface of the fin and the upper gate electrode;
a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate; and
an interface insulation layer disposed between a top surface of the dielectric layer and the gate electrode,
wherein the interface insulation layer has a thickness less than a thickness of the dielectric layer.
11. The compound semiconductor device of claim 1 , wherein the upper gate electrode directly contacts the second semiconductor layer.
12. The compound semiconductor device of claim 1 , wherein the dielectric layer has a thickness in a range from about 20 nm to about 100 nm.
13. A compound semiconductor device comprising:
a first semiconductor layer having a fin extending in a first direction on a substrate;
an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer;
second semiconductor layers disposed between sidewalls of the fin and the upper gate electrode; and
a dielectric layer disposed on a top surface of the fin and top surfaces of the second semiconductor layers,
wherein the second semiconductor layers are spaced apart from each other in the second direction and extend in parallel to each other in the first direction;
wherein the upper gate electrode directly contacts the second semiconductor layers.
14. The compound semiconductor device of claim 13 , wherein the second semiconductor layers have top surfaces disposed at a same vertical level as a top surface of the first semiconductor layer.
15. The compound semiconductor device of claim 13 , wherein each of the second semiconductor layers has a bandgap different from a bandgap of the first semiconductor layer.
16. The compound semiconductor device of claim 13 , further comprising a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate,
wherein the lower gate structure extends in the second direction.
17. The compound semiconductor device of claim 13 , further comprising an interface insulation layer disposed between a top surface of the dielectric layer and the gate electrode,
wherein the interface insulation layer has a thickness less than a thickness of the dielectric layer.
18. The compound semiconductor device of claim 13 , further comprising source and drain contacts spaced apart from each other in the first direction and connected to the first semiconductor layer,
wherein the upper gate electrode is disposed between the source and drain contacts.