Word line structure of three-dimensional memory device
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.
1. A memory device, comprising:
a substrate;
a stack structure on the substrate; and
at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions,
wherein the stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions, and wherein the at least one connection portion comprises at least two subsets of connection portions that are aligned along the first direction.
2. The memory device of claim 1 , wherein:
the stack structure includes a plurality of gate material layers and a plurality of insulating layers alternatingly arranged and extending along the first direction.
3. The memory device of claim 2 , wherein:
the stack structure includes a plurality of tiers that are pairs each including one of the plurality of gate material layers and one of the plurality of insulating layers.
4. The memory device of claim 3 , wherein the at least one connection portion comprises:
a plurality of groups of connection portions, each group of connection portions being conductively connected with one of the plurality of gate material layers of a same tier.
5. The memory device of claim 4 , wherein:
the plurality of tiers include a first tier and a second tier on the first tier, and
a first number of a first group of connection portions that conductively connect the gate material layer of the first tier is different from a second number of a second group of connection portions that conductively connect the gate material layer of the second tier.
6. The memory device of claim 5 , wherein the first number is greater than the second number.
7. The memory device of claim 2 , further comprising:
a plurality of metal contact vias, wherein the plurality of metal contact vias are each formed on one of the plurality of gate material layers.
8. The memory device of claim 2 , wherein:
the at least one connection portion is made of a material that is the same as a material of the plurality of gate material layers.
9. The memory device of claim 1 , further comprising:
a source region in the substrate; and
a source contact via formed in the at least one gate line slit and electrically connected to the source region, wherein
the at least two portions are electrically insulated from the source contact via.
10. A memory device, comprising:
a substrate;
a stack structure on the substrate;
at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions, wherein the stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions;
a source region in the substrate; and
a source contact via formed in the at least one gate line slit and electrically connected to the source region, wherein the at least two portions are electrically insulated from the source contact via.
11. The memory device of claim 10 , wherein:
the stack structure includes a plurality of gate material layers and a plurality of insulating layers alternatingly arranged and extending along the first direction.
12. The memory device of claim 11 , wherein:
the stack structure includes a plurality of tiers that are pairs each including one of the plurality of gate material layers and one of the plurality of insulating layers.
13. The memory device of claim 12 , wherein the at least one connection portion comprises:
a plurality of groups of connection portions, each group of connection portions being conductively connected with one of the plurality of gate material layers of a same tier.
14. The memory device of claim 13 , wherein:
the at least one connection portion comprises at least two subsets of connection portions that are aligned along the first direction.
15. The memory device of claim 14 , wherein:
the plurality of tiers include a first tier and a second tier on the first tier, and
a first number of a first group of connection portions that conductively connect the gate material layer of the first tier is different from a second number of a second group of connection portions that conductively connect the gate material layer of the second tier.
16. The memory device of claim 15 , wherein the first number is greater than the second number.
17. The memory device of claim 11 , further comprising:
a plurality of metal contact vias, wherein the plurality of metal contact vias are each formed on one of the plurality of gate material layers.
18. The memory device of claim 11 , wherein:
the at least one connection portion is made of a material that is the same as a material of the plurality of gate material layers.